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參數(shù)資料
| 型號： | AD524AE |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | Single Supply, Rail-to-Rail, Low Cost Instrumentation Amplifier |
| 中文描述： | INSTRUMENTATION AMPLIFIER, 250 uV OFFSET-MAX, 1 MHz BAND WIDTH, PQCC20 |
| 封裝： | LCC-20 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 364K |
| 代理商： | AD524AE |
REV. A
AD5241/AD5242
–6–
t
8
t
1
t
8
t
3
t
2
t
2
t
9
t
5
t
10
S
P
t
7
t
4
S
P
SDA
SCL
t
6
Figure 1. Detail Timing Diagram
Data of AD5241/AD5242 is accepted from the I
2
C bus in the following serial format:
S
0
1
0
1
1
AD1 AD0 R/
W
A
A
/B
RS
SD
O
1
O
2
X
X
X
A
D7
D6
D5
D4
D3
D2
D1
D0
A
P
SLAVE ADDRESS BYTE
INSTRUCTION BYTE
DATA BYTE
where:
S = Start Condition
P = Stop Condition
A = Acknowledge
X = Don’t Care
AD1, AD0 = Package pin programmable address bits. Must be matched with the logic states at pins AD1 and AD0.
R/
W
= Read Enable at High and output to SDA. Write Enable at Low.
A
/B = RDAC sub address select. ‘0’ for RDAC1 and ‘1’ for RDAC2.
RS = Midscale reset, active high.
SD = Shutdown in active high. Same as
SHDN
except inverse logic.
O
1
, O
2
= Output logic pin latched values.
D7, D6, D5, D4, D3, D2, D1, D0 = Data Bits.
1
9
1
1
9
9
0
1
0
1
1
AD1
AD0
R/
W
A
/B
RS
SD
O1
O2
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
AD5241
AD5241
AD5241
STOP BY
SMASTER
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
INSTRUCTION BYTE
FRAME 3
DATA BYTE
SCL
SDA
Figure 2. Writing to the RDAC Serial Register
1
9
1
9
0
1
0
1
1
AD1
AD0
R/
W
D7
D6
D5
D4
D3
D2
D1
D0
AD5241
NMASTER
STOP BY
SMASTER
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
DATA BYTE FROM PREVIOUSLY SELECTED
RDAC REGISTER IN WRITE MODE
SCL
SDA
Figure 3. Reading Data from a Previously Selected RDAC Register in Write Mode
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