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參數(shù)資料
| 型號(hào)： | AD5243EVAL |
| 廠商： | Analog Devices, Inc. |
| 元件分類(lèi)： | 數(shù)字電位計(jì) |
| 英文描述： | Dual 256-Position I2C Compatible Digital Potentiometer |
| 中文描述： | 雙256位I2C兼容數(shù)字電位器 |
| 文件頁(yè)數(shù)： | 5/20頁(yè) |
| 文件大?。?/td> | 798K |
| 代理商： | AD5243EVAL |
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AD5243/AD5248
TIMING CHARACTERISTICS—ALL VERSIONS
V
DD
= 5V ± 10%, or 3V ± 10%; V
A
= V
DD
; V
B
= 0 V; 40°C < T
A
< +125°C; unless otherwise noted.
Table 3.
Parameter
I
2
C INTERFACE TIMING CHARACTERISTICS
10
(Specifications Apply to All Parts)
SCL Clock Frequency
t
BUF
Bus Free Time between STOP and START
t
HD;STA
Hold Time (Repeated START)
Rev. 0 | Page 5 of 20
Symbol
Conditions
Min
0
1.3
0.6
Typ
1
Max
400
Unit
kHz
μs
μs
f
SCL
t
1
t
2
After this period, the first clock pulse is
generated.
t
LOW
Low Period of SCL Clock
t
HIGH
High Period of SCL Clock
t
SU;STA
Setup Time for Repeated START Condition
t
HD;DAT
Data Hold Time
11
t
SU;DAT
Data Setup Time
t
F
Fall Time of Both SDA and SCL Signals
t
R
Rise Time of Both SDA and SCL Signals
t
SU;STO
Setup Time for STOP Condition
See notes at end of section.
NOTES
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
1.3
0.6
0.6
100
0.6
0.9
300
300
μs
μs
μs
μs
ns
ns
ns
μs
1
Typical specifications represent average readings at 25°C and V
DD
= 5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
V
AB
= V
DD
, wiper (VW) = no connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
9
All dynamic characteristics use V
DD
= 5 V.
10
See timing diagrams for locations of measured values.
11
The maximum t
HD:DAT
must be met only if the device does not stretch the low period (t
LOW
) of the SCL signal.
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