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參數(shù)資料
| 型號： | AD5241BRUZ1M-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/20頁 |
| 文件大小： | 0K |
| 描述： | IC DGTL POT 256POS 14-TSSOP T/R |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 接片： | 256 |
| 電阻（歐姆）： | 1M |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 30 ppm/°C |
| 存儲(chǔ)器類型： | 易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V，±2.3 V ~ 2.7 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 帶卷 (TR) |
AD5241/AD5242
Rev. C | Page 15 of 20
ADDITIONAL PROGRAMMABLE LOGIC OUTPUT
The AD5241/AD5242 feature additional programmable logic
outputs, O1 and O2, that can be used to drive digital load, analog
switches, and logic gates. They can also be used as a self-contained
shutdown preset to Logic 0 that is further explained in the
power-up. The logic states of O1 and O2 can be programmed in
the output stage of O1, which employs large P-channel and N-
channel MOSFETs in push-pull configuration. As shown in
outputs have adequate current driving capability to drive
milliamperes of load.
IN
1
2
VDD
O1
VSS
MP
MN
O1 DATA IN FRAME 2
OF WRITE MODE
00
92
6-
0
25
Figure 34. Output Stage of Logic Output, O1
Users can also activate O1 and O2 in the following three different
ways without affecting the wiper settings:
1.
Start, slave address byte, acknowledge, instruction byte
with O1 and O2 specified, acknowledge, stop.
2.
Complete the write cycle with stop, then start, slave address
byte, acknowledge, instruction byte with O1 and O2 specified,
acknowledge, stop.
3.
Do not complete the write cycle by not issuing the stop,
then start, slave address byte, acknowledge, instruction
byte with O1 and O2 specified, acknowledge, stop.
All digital inputs are protected with a series input resistor and
the parallel Zener ESD structures shown in Figure 36. This
applies to the digital input pins, SDA, SCL, and SHDN.
SHUTDOWN FUNCTION
Shutdown can be activated by strobing the SHDN pin or
programming the SD bit in the write mode instruction byte (see
). If the RDAC Register 1 or RDAC Register 2 (AD5242
only) is placed in shutdown mode by the software, SD bit, the
part returns the wiper to its prior position when a new command
is received.
In addition, shutdown can be implemented with the device digital
output, as shown in Figure 35. In this configuration, the device
is shutdown during power-up but users are allowed to program
the device. Thus, when O1 is programmed high, the device exits
shutdown mode and responds to the new setting. This self-contained
shutdown function allows absolute shutdown during power-up,
which is crucial in hazardous environments, and it does not add
extra components.
SDA
SHDN
SCL
RPD
O1
0
09
26
-0
26
Figure 35. Shutdown by Internal Logic Output, O1
340
LOGIC
VSS
00
92
6-
0
27
Figure 36. ESD Protection of Digital Pins
A,B,W
VSS
0
092
6-
0
28
Figure 37. ESD Protection of Resistor Terminals
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