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參數(shù)資料
| 型號： | AD5233BRU50-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | 32-Tap. Nonvolatile. Linear-Taper Digital Potentiometers in SOT23 |
| 中文描述： | QUAD 50K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO24 |
| 封裝： | MO-153AD, TSSOP-24 |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 221K |
| 代理商： | AD5233BRU50-REEL7 |
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers
AD5231/AD5232/AD5233
Table 4. AD5232 Instruction/Operation Truth Table
Inst
No.
B15 B8
B7 B0
C3 C2 C1 C0 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
0
0 0 0 0 X X X X
X X X X X X X X
REV PrF
Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL(408)382-3107; FAX (408)382-2708; walt.heinzer@analog.com
10
22 MAR '01
Instruction Byte 1
Data Byte 0
Operation
No Operation (NOP): Do nothing
1
0 0 0 1 << ADDR >>
X X X X X X X X
Write contents of EEMEM(ADDR) to RDAC(ADDR)
Register
SAVE WIPER SETTING: Write contents of
RDAC(ADDR) to EEMEM(ADDR)
Write contents of Serial Register Data Byte 0 to
EEMEM(ADDR)
Decrement 6dB: Right Shift contents of
RDAC(ADDR) , stops at all "Zeros".
Decrement All 6dB: Right Shift contents of all
RDAC Registers, stops at all "Zeros".
Decrement contents of RDAC(ADDR) by "One",
stops at all "Zeros".
Decrement contents of all RDAC Registers by
"One", stops at all "Zeros".
RESET: Load all RDACs with their corresponding
EEMEM previously-saved values
Write contents of EEMEM(ADDR) to Serial Register
Data Byte 0
Write contents of RDAC(ADDR) to Serial Register
Data Byte 0
Write contents of Serial Register Data Byte 0 to
RDAC(ADDR)
Increment 6dB: Left Shift contents of
RDAC(ADDR), stops at all "Ones".
Increment All 6dB: Left Shift contents of all RDAC
Registers, stops at all "Ones".
Increment contents of RDAC(ADDR) by "One",
stops at all "Ones".
Increment contents of all RDAC Registers "One",
stops at all "Ones".
2
0 0 1 0 << ADDR >>
X X X X X X X X
3
0 0 1 1 << ADDR >>
D7 D6 D5 D4 D3 D2 D1 D0
4
0 1 0 0 << ADDR >>
X X X X X X X X
5
0 1 0 1 X X X X
X X X X X X X X
6
0 1 1 0 << ADDR >>
X X X X X X X X
7
0 1 1 1 X X X X
X X X X X X X X
8
1 0 0 0 0 0 0 0
X X X X X X X X
9
1 0 0 1 << ADDR >>
X X X X X X X X
10
1 0 1 0 << ADDR >>
X X X X X X X X
11
1 0 1 1 << ADDR >>
D7 D6 D5 D4 D3 D2 D1 D0
12
1 1 0 0 << ADDR >>
X X X X X X X X
13
1 1 0 1 X X X X
X X X X X X X X
14
1 1 1 0 << ADDR >>
X X X X X X X X
15
1 1 1 1 X X X X
X X X X X X X X
NOTES:
1. The SDO output shifts-out the last 8-bits of data clocked into the serial register for daisy chain operation. Exception:
following Instruction #9 or #10 the selected internal register data will be present in data byte 0. Instructions following #9
& #10 must be a full 16-bit data word to completely clock out the contents of the serial register.
2. The RDAC register is a volatile scratch pad register that is refreshed at power ON from the corresponding non-volatile
EEMEM register.
3. The increment, decrement and shift commands ignore the contents of the shift register Data Byte 0.
4. Execution of the Operation column noted in the table takes place when the
CS
strobe returns to logic high.
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