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參數資料
| 型號： | AD5233BRU100-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字電位計 |
| 英文描述： | Ceramic Disc Capacitor; Capacitance:0.1uF; Capacitance Tolerance: 20%; Series:UK; Termination:Radial Leaded; Dielectric Characteristic:Y5P; Features:Low-Voltage |
| 中文描述： | QUAD 100K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO24 |
| 封裝： | MO-153AD, TSSOP-24 |
| 文件頁數： | 3/14頁 |
| 文件大小： | 221K |
| 代理商： | AD5233BRU100-REEL7 |
PRELIMINARY TECHNICAL DATA
AD5231/AD5232/AD5233 -
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS 10K, 50K, 100K OHM VERSIONS
(V
DD
= +3V±10% to +5V±10% and V
SS
=0V,
V
= +V
, V
B
= 0V, -40°C < T
A
< +85°C unless otherwise noted.)
Parameter
Symbol Conditions
REV PrF
Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL(408)382-3107; FAX (408)382-2708; walt.heinzer@analog.com
3
22 MAR '01
Min
Typ
1
Max
Units
INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 5, 9)
Clock Cycle Time
Input Clock Pulse Width
CS
Setup Time
Data Setup Time
Data Hold Time
CLK Shutdown Time
CS
Rise to Clock Rise Setup
CS
High Pulse Width
CLK to SDO Propagation Delay
10
Store to Nonvolatile EEMEM Save Time
11
CS
to SDO - SPI line acquire
CS
to SDO - SPI line release
RDY Rise to
CS
Fall
Startup Time
CLK Setup Time
Preset Pulse Width (Asynchronous)
Preset Response Time
t
1
t
2
, t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
12
t
13
t
14
t
15
t
16
t
17
t
PR
t
PRESP
Clock level high or low
From Positive CLK transition
From Positive CLK transition
R
P
= 1K
, C
L
< 20pF
Applies to Command 2
H
, 3
H
, 9
H
For 1 CLK period (t
4
- t
3
= 1 CLK period)
PR
pulsed low then high
20
10
10
5
5
0
10
10
1
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ms
ns
ns
us
25
25
70
NOTES:
1.
2.
Typicals represent average readings at +25°C and V
DD
= +5V.
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the
relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I
W
= V
DD
/R for both V
DD
=+3V or V
DD
=+5V.
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= V
SS
.
DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions.
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
Guaranteed by design and not subject to production test.
Common mode leakage current is a measure of the DC leakage from any terminal A, B, W to a common mode bias level of V
DD
/ 2.
P
DISS
is calculated from (I
DD
x V
DD
) + (I
SS
X V
SS
).
All dynamic characteristics use V
DD
= +5V.
See timing diagram for location of measured values. All input control voltages are specified with t
R
=t
F
=2.5ns(10% to 90% of 3V) and timed from a voltage level of 1.5V. Switching
characteristics are measured using both V
DD
= +3V or +5V.
Propagation delay depends on value of V
DD
, R
PULL_UP
, and C
L
see applications text.
Low only for instruction commands 8, 9,10, 2, 3: CMD_8 ~ 1ms; CMD_9,10 ~0.12ms; CMD_2,3 ~20ms
Dual Supply Operation primarily affects the POT terminals.
Read Mode current is not continuous.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
Timing Diagram
t
2
t
3
MSB
LSB
MSB
LSB
CLK
CS
SDI
SDO
1
t
1
t
4
t
5
t
6
t
7
t
9
t
14
t
10
RDY
t
12
t
17
MSB
LSB
SDO
2
t
13
t
15
t
16
SDO
1
CLK IDLES LOW
SDO
2
CLK IDLES HIGH
Figure 1. Timing Diagram
t
8
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| AD5233BRU10-REEL7 | 制造商:Analog Devices 功能描述:Digital Potentiometer 64POS 10KOhm Quad 24-Pin TSSOP T/R 制造商:Rochester Electronics LLC 功能描述:QUAD 6BIT EEMEM DIG POT - Tape and Reel |
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