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參數(shù)資料
| 型號： | AD5232BRUZ100-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT DUAL 256POS 16-TSSOP |
| 標準包裝： | 1,000 |
| 接片： | 256 |
| 電阻（歐姆）： | 100k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標準值 600 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | 4 線 SPI（芯片選擇） |
| 電源電壓： | 2.7 V ~ 5.5 V，±2.25 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-AD5232-10EBZ-ND - BOARD EVALUATION FOR AD5232-10 |
AD5232
Data Sheet
Rev. C | Page 4 of 24
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DYNAMIC CHARACTERISTICS5, 9
Bandwidth
3 dB, BW_10k, R = 10 k
500
kHz
Total Harmonic Distortion
THDw
VA = 1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 k
0.022
%
VA = 1 V rms, VB = 0 V, f = 1 kHz, RAB = 50 k, 100 k
0.045
%
VW Settling Time
tS
VDD = 5 V, VSS = 0 V, VA = VDD, VB = 0 V,
0.65/3/6
s
VW = 0.50% error band, Code 0x00 to Code 0x80
for RAB = 10 k/50 k/100 k
Resistor Noise Voltage
eN_WB
RWB = 5 k, f= 1 kHz
9
nV/√Hz
Crosstalk (CW1/CW2)
CT
VA = VDD, VB = 0 V, measure VW with
5
nV-sec
adjacent VR making full-scale code change
Analog Crosstalk (CW1/CW2)
CTA
VA1 = VDD, VB1 = 0 V, measure VW1 with VW2 =
70
dB
5 V p-p @ f = 10 kHz; Code1 = 0x80; Code2 = 0xFF
FLASH/EE MEMORY RELIABILITY
Endurance10
100
kCycles
Data Retention11
100
Years
1
Typical parameters represent average readings at 25°C and VDD = 5 V.
2
Resistor position nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. IW ~ 50 A @ VDD = 2.7 V and IW ~
400 A @ VDD = 5 V for the RAB = 10 k version, IW ~ 50 A for the RAB = 50 k version, and IW ~ 25 A for the RAB = 100 k version (see Figure 22).
3
INL and DNL are measured at VW with the RDACx configured as a potentiometer divider similar to a voltage output digital-to-analog converter. VA = VDD and VB = VSS.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions (see Figure 23).
4
The A, B, and W resistor terminals have no limitations on polarity with respect to each other. Dual supply operation enables ground-referenced bipolar signal
adjustment.
5
Guaranteed by design; not subject to production test.
6
Common-mode leakage current is a measure of the dc leakage from any A, B, or W terminal to a common-mode bias level of VDD/2.
7
Transfer (XFR) mode current is not continuous. Current is consumed while the EEMEMx locations are read and transferred to the RDACx register (see Figure 13).
8
PDISS is calculated from (IDD × VDD) + (ISS × VSS).
9
All dynamic characteristics use VDD = +2.5 V and VSS = 2.5 V, unless otherwise noted.
10
Endurance is qualified to 100,000 cycles per JEDEC Std. 22, Method A117 and measured at 40°C, +25°C, and +85°C. Typical endurance at +25°C is 700,000 cycles.
11
The retention lifetime equivalent at junction temperature (TJ) = 55°C, as per JEDEC Std. 22, Method A117. Retention lifetime, based on an activation energy of 0.6 eV,
derates with junction temperature as shown in Figure 44 in the Flash/EEMEM Reliability section. The AD5232 contains 9,646 transistors. Die size = 69 mil × 115 mil,
7,993 sq. mil.
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