參數(shù)資料
型號(hào)： AD5232BRU50-REEL7
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字電位計(jì)
英文描述： 8-Bit Dual Nonvolatile Memory Digital Potentiometer
中文描述： DUAL 50K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO16
封裝： MO-153AB, TSSOP-16
文件頁數(shù)： 3/20頁
文件大小： 268K
代理商： AD5232BRU50-REEL7
–3–
REV. 0
nV/
√
Hz
Parameter
DYNAMIC CHARACT ERIST ICS
5, 9
Bandwidth
T otal Harmonic Distortion
Symbol
Conditions
Min
T yp
1
Max
Unit
–3 dB, BW_10 k
, R = 10 k
V
A
= 1 V rms, V
B
= 0 V, f = 1 kHz,
R
AB
= 10 k
V
A
=1 V rms, V
B
= 0 V, f = 1 kHz,
R
AB
= 50 k
, 100 k
V
DD
= 5 V, V
SS
= 0 V, V
A
= V
DD
, V
B
= 0 V,
V
W
= 0.50% Error Band, Code 00
H
to
80
H
For R
AB
= 10 k
/50 k
/100 k
R
WB
= 5 k
, f = 1 kHz
Crosstalk (C
W1
/C
W2
)
V
A
= V
DD
, V
B
= 0 V, Measure V
W
with
Adjacent VR Making Full-Scale Code Change
V
A1
= V
DD
, V
B1
= 0 V, Measure V
W1
with V
W2
= 5 V p-p @ f = 10 kHz,
Code
1
= 80
H
;
Code
2
= FF
H
500
kHz
T HD
W
0.022
%
T HD
W
0.045
%
V
W
Settling T ime
t
S
0.65/3/6
9
μ
s
Resistor Noise Voltage
e
N_WB
C
T
–5
nV-s
Analog Crosstalk (C
W1
/C
W2
)
C
T A
–70
dB
INT ERFACE T IMING CHARACTERISTICS – Applies to All Parts
5, 10
Clock Cycle T ime (t
CYC
)
CS
Setup T ime
CLK Shutdown T ime to
CS
Rise
Input Clock Pulsewidth
Data Setup T ime
Data Hold T ime
CS
to SDO-SPI Line Acquire
CS
to SDO-SPI Line Release
CLK to SDO Propagation Delay
11
CLK to SDO Data Hold T ime
CS
High Pulsewidth
12
CS
High to
CS
High
12
RDY Rise to
CS
Fall
CS
Rise to RDY Fall T ime
Read/Store to Nonvolatile EEMEM
13
CS
Rise to Clock Rise/Fall Setup
Preset Pulsewidth (Asynchronous)
Preset Response T ime to RDY High t
PRESP
t
1
t
2
t
3
t
4
, t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
PRW
20
10
1
10
5
5
ns
ns
t
CYC
ns
ns
ns
ns
ns
ns
ns
ns
t
CYC
ns
ms
ms
ns
ns
Clock Level High or Low
From Positive CLK T ransition
From Positive CLK T ransition
40
50
50
R
P
= 2.2 k
, C
L
< 20 pF
R
P
= 2.2 k
, C
L
< 20 pF
0
10
4
0
0.1
0.15
25
Applies to Command 2
H
, 3
H
, 9
H
10
50
Not Shown in T iming Diagram
PR
Pulsed Low to Refreshed
Wiper Positions
70
μ
s
FLASH/EE MEMORY RELIABILIT Y CHARACT ERIST ICS
Endurance
14
Data Retention
15
100
K Cycles
Years
100
NOT ES
T ypical parameters represent average readings at 25
°
C and V
= 5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
postions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I
~ 50
μ
A @ V
DD
= 2.7 V and
I
~400
μ
A @ V
= 5 V for the R
= 10 k
version, I
~ 50
μ
A for the R
= 50 k
and I
~
25
μ
A for the R
= 100 k
version. See Figure 13.
3
INL and DNL are measured at V
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= V
SS
. DNL
specification limits of
±
1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 14.
4
Resistor terminals A, B, W have no limitations on polarity with respect to each other. Dual Supply Operation enables ground-referenced bipolar signal adjustment.
5
Guaranteed by design and not subject to production test.
6
Common-mode leakage current is a measure of the dc leakage from any terminal A, B, W to a common-mode bias level of V
/2.
7
T ransfer (X FR) Mode current is not continuous. Current consumed while EEMEM locations are read and transferred to the RDAC register. See T PC 9.
8
P
is calculated from (I
V
DD
) + (I
V
).
9
All dynamic characteristics use V
= +2.5 V and V
= –2.5 V unless otherwise noted.
10
See timing diagram for location of measured values. All input control voltages are specified with t
R
= t
F
= 2.5 ns (10% to 90% of 3 V) and timed from a voltage level
of 1.5 V. Switching characteristics are measured using both V
DD
= 3 V or 5 V.
11
Propagation delay depends on value of V
, R
, and C
L
. See applications text.
12
Valid for commands that do not activate the RDY pin.
13
RDY pin low only for instruction commands 8, 9, 10, 2, 3, and the
PR
hardware pulse: CMD_8 ~ 1 ms; CMD_9,10 ~ 0.12 ms; CMD_2,3 ~ 20 ms. Device operation
at T
= –40
°
C and V
< 3 V extends the save time to 35 ms.
14
Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at V
DD
= 2.7 V, T
A
= –40
°
C to +85
°
C, typical endurance at 25
°
C is
700,000 cycles.
15
Retention lifetime equivalent at junction temperature (T
) = 55
°
C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV
will derate with junction temperature as shown in Figure 23 in the Flash/EE Memory description section of this data sheet. T he AD5232 contains 9,646
transistors. Die size: 69 mil 115 mil, 7,993 sq. mil.
Specifications subject to change without notice
AD5232
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