參數(shù)資料
型號: AD5232BRU10
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字電位計
英文描述: 8-Bit Dual Nonvolatile Memory Digital Potentiometer
中文描述: DUAL 10K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO16
封裝: MO-153AB, TSSOP-16
文件頁數(shù): 15/20頁
文件大小: 268K
代理商: AD5232BRU10
REV. 0
AD5232
–15–
~
OFFSET BIAS
OFFSET
GND
A
B
DUT
W
5V
V
IN
V
OUT
OP279
Figure 18. Noninverting Gain Test Circuit
~
OFFSET
GND
A
B
DUT
W
+15V
V
IN
V
OUT
OP42
15V
2.5V
Figure 19. Gain vs. Frequency Test Circuit
+
_
DUT
CODE = OO
H
0.1V
V
SS
TO V
DD
R
SW
= I
SW
I
SW
W
B
Figure 20. Incremental ON Resistance Test Circuit
DUT
V
SS
I
CM
W
B
V
NC
NC
V
CM
GND
A
NC = NO CONNECT
Figure 21. Common-Mode Leakage Current Test Circuit
W2
B2
V
DD
A2
~
V
IN
NC
W1
RDAC
1
A1
B1 V
SS
V
OUT
RDAC
2
C
TA
= 20 log [V
OUT
/V
IN
]
Figure 22. Analog Crosstalk Test Circuit
Flash/E E ME M Reliability
T he Flash/EE Memory array on the AD5232 is fully qualified
for two key Flash/EE memory characteristics, namely Flash/EE
Memory C ycling Endurance and F lash/EE Memory Data
Retention.
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many Program, Read, and Erase cycles. In real
terms, a single endurance cycle is composed of four indepen-
dent, sequential events. T hese events are defined as:
a. Initial page erase sequence
b. Read/verify sequence
c. Byte program sequence
d. Second read/verify sequence
During reliability qualification Flash/EE memory is cycled from
00
H
to FF
H
until a first fail is recorded, signifying the endurance
limit of the on-chip Flash/EE memory.
As indicated in the specification pages of this data sheet, the
AD5232 Flash/EE Memory Endurance qualification has been
carried out in accordance with JEDEC Specification A117 over
the industrial temperature range of –40
°
C to +85
°
C. T he results
allow the specification of a minimum endurance figure over supply
and temperature of 100,000 cycles, with an endurance figure of
700,000 cycles being typical of operation at 25
°
C.
Retention quantifies the ability of the Flash/EE memory to retain
its programmed data over time. Again, the AD5232 has been
qualified in accordance with the formal JEDEC Retention Life-
time Specification (A117) at a specific junction temperature
(T
J
= 55
°
C). As part of this qualification procedure, the Flash/EE
memory is cycled to its specified endurance limit described above,
before data retention is characterized. T his means that the Flash/EE
memory is guaranteed to retain its data for its full-specified reten-
tion lifetime every time the Flash/EE memory is reprogrammed. It
should also be noted that retention lifetime, based on an activa-
tion energy of 0.6 eV, will derate with T
J
as shown in Figure 23.
T
J
JUNCTION TEMPERATURE
C
300
250
0
40
R
200
150
100
50
50
60
70
80
90
100
110
ADI TYPICAL
PERFORMANCE
AT
T
J
= 55 C
Figure 23. Flash/EE Memory Data Retention
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