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參數(shù)資料
| 型號： | AD5232BRU100 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | 8-Bit Dual Nonvolatile Memory Digital Potentiometer |
| 中文描述： | DUAL 100K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO16 |
| 封裝： | MO-153AB, TSSOP-16 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 268K |
| 代理商： | AD5232BRU100 |
REV. 0
AD5232
–11–
USING ADDIT IONAL INT E RNAL NONVOLAT ILE E E ME M
T he AD5232 contains additional internal user storage registers
(EEMEM) for saving constants and other 8-bit data. T able IV
provides an address map of the internal nonvolatile storage
registers shown in the functional block diagram as EEMEM1,
EEMEM2, and bytes of USER EEMEM.
T able IV. E E ME M Address Map
E E ME M Contents of E ach
Device E E ME M (ADDR)
AD5232 (8B)
RDAC1
RDAC2
USER 1
USER 2
USER 3
USER 4
***
USER 14
E E ME M
Address
(ADDR)
0000
0001
0010
0011
0100
0101
***
1111
NOT ES
1
RDAC data stored in EEMEM locations are transferred to their
corresponding RDAC REGIST ER at Power ON, or when
instructions Inst#1 and Inst#8 are executed.
2
USER <data> is internal nonvolatile EEMEM registers available
to store and retrieve constants using Inst#3 and Inst#9 respectively.
3
AD5232 EEMEM locations are 1 byte each (8 bits).
4
Execution of instruction #1 leaves the device in the Read Mode power con-
sumption state. After the last Instruction #1 is executed, the user should
perform a NOP, Instruction #0 com mand to return the device to the low
power idle state.
V
DD
A
W
B
V
SS
Figure 8. Maximum Terminal Voltages Set by V
DD
and V
SS
DETAIL POTENTIOMETER OPERATION
T he actual structure of the RDAC is designed to emulate the
performance of a mechanical potentiometer. T he patent-pending
RDAC contains multiple strings of connected resistor segments,
with an array of analog switches that act as the wiper connection
to several points along the resistor array. T he number of points
is the resolution of the device. For example, the AD5232 has
256 connection points allowing it to provide better than 0.5%
setability resolution. Figure 9 provides an equivalent dia-
gram of the connections between the three terminals that
make up one channel of the RDAC. T he SW
A
and SW
B
will
always be ON, while one of the switches SW(0) to SW(2
N
–1)
will be ON one at a time depending upon the resistance step
decoded from the Data Bits. T he resistance contributed by R
W
must be accounted for in the output resistance. T he SW
A
and
SW
B
will always be ON while one of the switches SW(0) to
SW(2
N
–1) will be ON one at a time, depending upon the
resistance step decoded from the Data Bits. T he resistance
contributed by R
W
must be accounted for in the output resistance.
SW
A
SW(2
N
–
1)
A
X
W
X
SW(2
N
–
2)
SW
(1)
SW
(0)
SW
B
B
X
RDAC
WIPER
REGISTER
AND
DECODER
R
S
=
R
AB
/2
N
R
S
R
S
R
S
DIGITAL
CIRCUITRY
OMITTED FOR
CLARITY
Figure 9. Equivalent RDAC Structure (Patent Pending)
T able V. RDAC and Digital Register Address Map
Register Address
(ADDR)
0000
0001
Name of Register
*
AD5232 (8B)
RDAC1
RDAC2
*
RDACx registers contain data determining the
position of the variable resistor wiper.
T E RMINAL VOLT AGE OPE RAT ING RANGE
T he digital potentiometer’s positive V
DD
and negative V
SS
power
supply defines the boundary conditions for proper three-terminal
programmable resistance operation. Signals present on terminals
A, B, W that exceed V
DD
or V
SS
will be clamped by a forward
biased diode; see Figure 8.
T he ground pin of the AD5232 device is primarily used as a
digital ground reference, which needs to be tied to the PCBs’
common ground. T he digital input logic signals to the AD5232
must be referenced to the devices’ ground pin (GND), and
satisfy the logic minimum input high level and the maximum
low level defined in the specification table of this data sheet.
An internal level-shift circuit between the digital interface and
the wiper switch control ensures that the common-mode voltage
range of the three-terminals A, W, and B extends from V
SS
to V
DD
.
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