參數(shù)資料
型號(hào): AD5228BUJZ10-RL7
廠商: ANALOG DEVICES INC
元件分類(lèi): 數(shù)字電位計(jì)
英文描述: 32-Position Manual Up/Down Control Potentiometer
中文描述: 10K DIGITAL POTENTIOMETER, PUSH-BUTTON CONTROL INTERFACE, 32 POSITIONS, PDSO8
封裝: 2.90 X 3 MM, ROHS COMPLIANT, MO-193BA,TSOT-23, 8 PIN
文件頁(yè)數(shù): 4/20頁(yè)
文件大?。?/td> 341K
代理商: AD5228BUJZ10-RL7
AD5228
Parameter
DYNAMIC CHARACTERISTICS
4, 9, 10, 11
Built-in Debounce and Settling Time
12
PU Low Pulse Width
PD Low Pulse Width
PU High Repetitive Pulse Width
PD High Repetitive Pulse Width
Autoscan Start Time
Autoscan Time
Bandwidth –3 dB
Total Harmonic Distortion
Rev. 0 | Page 4 of 20
Symbol
t
DB
t
PU
t
PD
t
PU_REP
t
PD_REP
t
AS_START
t
AS
BW_10
BW_50
BW_100
THD
Conditions
PU or PD = 0 V
PU or PD = 0 V
R
AB
= 10 k, midscale
R
AB
= 50 k, midscale
R
AB
= 100 k, midscale
V
A
= 1 V rms, R
AB
= 10 k,
V
B
= 0 V dc, f = 1 kHz
R
WB
= 5 k, f = 1 kHz
Min
6
12
12
1
1
0.6
0.16
Typ
1
0.8
0.25
460
100
50
0.05
Max
1.2
0.38
Unit
ms
ms
ms
μs
μs
s
s
kHz
kHz
kHz
%
Resistor Noise Voltage
e
N_WB
14
nV/
Hz
1
Typicals represent average readings at 25°C, V
DD
= 5 V.
2
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
4
Guaranteed by design and not subject to production test.
5
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
6
Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.
7
PU and PD have 100 k internal pull-up resistors, I
DD_ACT
= V
DD
/100 k + I
OSC
(internal oscillator operating current) when PU or PD is connected to ground.
8
P
DISS
is calculated based on I
DD_STBY
× V
DD
only. I
DD_ACT
duration should be short. Users should not hold PU or PD pin to ground longer than necessary to elevate power
dissipation.
9
Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
10
All dynamic characteristics use V
DD
= 5 V.
11
Note that all input control voltages are specified with t
R
= t
F
= 1 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V. Switching characteristics are measured
using V
DD
= 5 V.
12
The debouncer keeps monitoring the logic-low level once PU is connected to ground. Once the signal lasts longer than 11 ms, the debouncer assumes the last
bounce is met and allows the AD5228 to increment by one step. If the PU signal remains at low and reaches t
AS_START
, the
AD5528 increments again, see Figure 7. Similar
characteristics apply to PD operation.
INTERFACE TIMING DIAGRAMS
0
R
WB
PU
t
DB
t
PU
t
PU_REP
Figure 2. Increment R
WB
in Discrete Steps
0
R
WB
PU
t
DB
t
AS
t
AS_START
Figure 3. Increment R
WB
in Autoscan Mode
0
R
WB
PU
t
DB
t
PD
t
PD_REP
Figure 4. Decrement R
WB
in Discrete Steps
0
R
WB
PD
DB
t
AS
t
AS_START
Figure 5. Decrement R
WB
in Autoscan Mode
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