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參數(shù)資料
| 型號： | AD5227EVAL |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | 64-Position Up/Down Control Digital Potentiometer |
| 中文描述： | 64工位上/下控制數(shù)字電位器 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 331K |
| 代理商： | AD5227EVAL |
AD5227
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. 0 | Page 6 of 16
0
AD5227
TOP VIEW
(Not to Scale)
CLK
1
U/D
2
A
3
GND
4
V
DD
CS
B
W
8
7
6
5
Figure 5. SOT-23-8 Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
1
CLK
Description
Clock Input. Each clock pulse executes the step-up or step-down of the resistance. The direction is determined
by the state of the U/D pin. CLK is a negative-edge trigger. Logic high signal can be higher than V
DD
, but lower
than 5.5 V.
Up/Down Selections. Logic 1 selects up and Logic 0 selects down. U can be higher than V
DD
, but lower than 5.5 V.
Resistor Terminal A. GND ≤ V
A
≤ V
DD
.
Common Ground.
Wiper Terminal W. GND ≤ V
W
≤ V
DD
.
Resistor Terminal B. GND ≤ V
B
≤ V
DD
.
Chip Select. Active Low. Logic high signal can be higher than V
DD
, but lower than 5.5 V.
Positive Power Supply, 2.7 V to 5.5 V.
2
3
4
5
6
7
8
U/D
A
GND
W
B
CS
V
DD
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