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參數(shù)資料
| 型號： | AD5222BR10 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 音頻控制 |
| 英文描述： | Increment/Decrement Dual Digital Potentiometer |
| 中文描述： | 2 CHANNEL(S), VOLUME CONTROL CIRCUIT, PDSO14 |
| 封裝： | SOIC-14 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 173K |
| 代理商： | AD5222BR10 |
–2–
REV. 0
AD5222–SPECIFICATIONS
Parameter
DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)
Resistor Differential NL
2
Resistor Nonlinearity
2
Nominal Resistor Tolerance
Resistance Temperature Coefficient
Wiper Resistance
3
Nominal Resistance Match
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs)
Resolution
N
Integral Nonlinearity
4
INL
INL
Differential Nonlinearity
4
DNL
Voltage Divider Temperature Coefficient
V
W
/
T
Full-Scale Error
V
WFSE
Zero-Scale Error
V
WZSE
RESISTOR TERMINALS
Voltage Range
5
V
A, B, W
Capacitance
6
A, B
C
A, B
Capacitance
6
W
C
W
Common-Mode Leakage
I
CM
DIGITAL INPUTS AND OUTPUTS
Input Logic High
V
IH
Input Logic Low
V
IL
Input Current
I
IL
Input Capacitance
6
C
IL
POWER SUPPLIES
Power Single-Supply Range
V
DD RANGE
Power Dual-Supply Range
V
DD/SS RANGE
Positive Supply Current
I
DD
Negative Supply Current
I
SS
Power Dissipation
7
P
DISS
Power Supply Sensitivity
PSS
DYNAMIC CHARACTERISTICS
6, 8, 9
Bandwidth –3 dB
BW_10K
BW_50K
BW_100K
BW_1M
Total Harmonic Distortion
THD
W
V
Settling Time
t
S
Resistor Noise Voltage
e
N_WB
INTERFACE TIMING CHARACTERISTICS (Applies to All Parts)
6, 10
Input Clock Pulsewidth
t
CH
, t
CL
CS
to CLK Setup Time
t
CSS
CS
Rise to CLK Hold Time
t
CSH
U/
D
to Clock Fall Setup Time
t
UDS
U/
D
to Clock Fall Hold Time
t
UDH
DACSEL to Clock Fall Setup Time
t
DSS
DACSEL to Clock Fall Hold Time
t
DSH
MODE to Clock Fall Setup Time
t
MDS
MODE to Clock Fall Hold Time
t
MDH
(V
DD
= 3 V
6
10% or 5 V
6
10%, V
SS
= 0 V, V
A
= +V
DD
, V
B
= 0 V, –40
8
C < T
A
< +85
8
C,
unless otherwise noted.)
Symbol
Condition
Min
Typ
1
Max
Unit
R-DNL
R-INL
R
R
AB
/
T
R
R/R
O
R
WB
, V
A
= NC
R
WB
, V
A
= NC
V
AB
= V
DD
, Wiper = No Connect, T
A
= 25
°
C
V
AB
= V
DD
, Wiper = No Connect
I
= V
/R, V
DD
= 3 V or 5 V
CH 1 to 2, V
AB
DD
, T
A
= 25
°
C
–1
–1
–30
±
1/4
±
0.4 +1
+1
LSB
LSB
%
ppm/
°
C
%
+30
–35
45
0.2
100
1
7
–1
–2
–1
Bits
LSB
LSB
LSB
ppm/
°
C
LSB
LSB
R
AB
= 10 k
, 50 k
, or 100 k
R
AB
= 1 M
±
1/4
±
1/2
±
1/4
20
–0.5
0.5
+1
+2
+1
Code = 40
H
Code = 7F
H
Code = 00
H
–1
0
+0
1
V
SS
V
DD
V
pF
pF
nA
f = 1 MHz, Measured to GND, Code = 40
H
f = 1 MHz, Measured to GND, Code = 40
H
V
A
= V
B
= V
W
45
60
1
V
DD
= 5 V/3 V
V
DD
= 5 V/3 V
V
IN
= 0 V or 5 V
2.4/2.1
V
0.8/0.6 V
±
1
μ
A
pF
5
V
SS
= 0 V
2.7
±
2.3
5.5
±
2.7
40
40
400
V
V
μ
A
μ
A
μ
W
%/%
V
IH
= 5 V or V
IL
= 0 V
V
SS
= –2.5 V, V
DD
= +2.7 V
V
IH
= 5 V or V
IL
DD
= 5 V
15
15
150
0.002 0.05
R
AB
= 10 k
, Code = 40
H
R
AB
= 50 k
, Code = 40
H
R
AB
= 100 k
, Code = 40
H
R
AB
= 500 k
, Code = 40
V
A
= 1 V rms + 2 V dc, V
B
= 2 V dc, f = 1 kHz
R
AB
= 10 k
,
±
1 LSB Error Band
R
WB
= 5 k
, f = 1 kHz
1000
180
78
7
0.005
2
14
kHz
kHz
kHz
kHz
%
μ
s
nV
√
Hz
Clock Level High or Low
30
20
20
10
30
20
30
20
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
1
Typicals represent average readings at 25
°
C, V
= 5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 22 test circuit.
3
Wiper resistance is not measured on the R
= 1 M
models.
4
INL and DNL are measured at V
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V. DNL
specification limits of
±
1 LSB maximum are guaranteed monotonic operating conditions. See Figure 21 test circuit.
5
Resistor Terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
P
is calculated from (I
×
V
). CMOS logic level inputs result in minimum power dissipation.
8
Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth.
The highest R value results in the minimum overall power consumption.
9
All dynamic characteristics use V
= 5 V.
10
See timing diagram for location of measured values. All input control voltages are specified with t
R
= t
F
= 2.5 ns (10% to 90% of +3 V) and timed from a voltage level
of 1.5 V. Switching characteristics are measured using both V
DD
= 5 V or V
DD
= 3 V.
Specifications subject to change without notice.
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| AD5222BR100 | 制造商:Analog Devices 功能描述:Digital Potentiometer 128POS 100KOhm Dual 14-Pin SOIC N 制造商:Rochester Electronics LLC 功能描述:7-BIT RDAC WITH UP/DWN CONTROL - Bulk |
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| AD5222BR1M | 制造商:Analog Devices 功能描述:Digital Potentiometer 128POS 1MOhm Dual 14-Pin SOIC N 制造商:Rochester Electronics LLC 功能描述:7-BIT RDAC WITH UP/DWN CONTROL - Bulk |
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