參數(shù)資料
型號(hào): AD5220
廠商: Analog Devices, Inc.
元件分類: 數(shù)字電位計(jì)
英文描述: Increment/Decrement Digital Potentiometer(增量/減量數(shù)字電位器)
中文描述: 遞增/遞減數(shù)字電位器(增量/減量數(shù)字電位器)
文件頁數(shù): 3/10頁
文件大小: 284K
代理商: AD5220
AD5220
–3–
REV. 0
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25
°
C, unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +7 V
V
A
, V
B
, V
W
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V
DD
A
X
–B
X
, A
X
–W
X
, B
X
–W
X
. . . . . . . . . . . . . . . . . . . . . .
±
20 mA
Digital Input Voltage to GND . . . . . . . . . . . 0 V, V
DD
+ 0.3 V
Operating Temperature Range . . . . . . . . . . . –40
°
C to +85
°
C
Maximum Junction Temperature (T
J
MAX) . . . . . . . .+150
°
C
Storage Temperature . . . . . . . . . . . . . . . . . . –65
°
C to +150
°
C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300
°
C
Package Power Dissipation . . . . . . . . . . . . . . (T
J
max–T
A
)/
θ
JA
Thermal Resistance
θ
JA
P-DIP (N-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
°
C/W
SOIC (SO-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
°
C/W
μ
SOIC (RM-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
°
C/W
*Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5220 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
CLK
U/
D
A1
GND
V
DD
CS
B1
W1
AD5220
t
CSS
t
CL
t
CH
t
CSH
t
UDS
1
0
1
0
1
0
CS
CLK
U/
D
Figure 3. Detail Timing Diagram
ORDERING GUIDE
Model
k
V
Temperature Range
Package Descriptions
Package Options
AD5220BN10
AD5220BR10
AD5220BRM10
AD5220BN50
AD5220BR50
AD5220BRM50
AD5220BN100
AD5220BR100
AD5220BRM100
10
10
10
50
50
50
100
100
100
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
8-Lead Plastic DIP
8-Lead (SOIC)
8-Lead
μ
SOIC
8-Lead Plastic DIP
8-Lead (SOIC)
8-Lead
μ
SOIC
8-Lead Plastic DIP
8-Lead (SOIC)
8-Lead
μ
SOIC
N-8
SO-8
RM-8
N-8
SO-8
RM-8
N-8
SO-8
RM-8
NOTE
The AD5220 die size is 37 mil
×
54 mil, 1998 sq mil; 0.938 mm
×
1.372 mm, 1.289 sq mm. Contains 754 transistors. Patent Number 5495245 applies.
Table I. Truth Table
CS
CLK
U/
D
Operation
L
L
H
t
t
X
H
L
X
Wiper Increment Toward Terminal A
Wiper Decrement Toward Terminal B
Wiper Position Fixed
PIN FUNCTION DESCRIPTIONS
Pin
No.
Name
Description
1
2
3
4
5
6
7
8
CLK
U/
D
A1
GND
W1
B1
CS
V
DD
Serial Clock Input, Negative Edge Triggered
UP/DOWN Direction Increment Control
Terminal A1
Ground
Wiper Terminal
Terminal B1
Chip Select Input, Active Low
Positive Power Supply
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