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參數(shù)資料
| 型號(hào)： | AD5206BN50 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字電位計(jì) |
| 英文描述： | 32-Tap. Nonvolatile. Linear-Taper Digital Potentiometers in SOT23 |
| 中文描述： | HEX 50K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDIP24 |
| 封裝： | PLASTIC, MS-001, DIP-24 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 173K |
| 代理商： | AD5206BN50 |
AD5204/AD5206
–8–
REV. 0
OPERATION
The AD5204/AD5206 provides a four-/six-channel, 256-position
digitally-controlled variable resistor (VR) device. Changing the
programmed VR settings is accomplished by clocking in a 11-
bit serial data word into the SDI (Serial Data Input) pin. The
format of this data word is three address bits, MSB first, fol-
lowed by eight data bits, MSB first. Table I provides the serial
register data word format.
Table I. Serial-Data Word Format
ADDR
B10 B9
DATA
B7
B8
B6
B5
B4
B3
B2
B1
B0
A2
MSB
2
10
A1
A0
LSB
2
8
D7
MSB
2
7
D6
D5
D4
D3
D2
D1
D0
LSB
2
0
See Table IV for the AD5204/AD5206 address assignments to
decode the location of VR latch receiving the serial register data
in Bits B7 through B0. VR outputs can be changed one at a
time in random sequence. The AD5204 presets to a midscale by
asserting the PR pin, simplifying fault condition recovery at
power up. Both parts have an internal power ON preset that
places the wiper in a preset midscale condition at power ON. In
addition, the AD5204 contains a power shutdown SHDN pin
which places the RDAC in a zero power consumption state
where Terminals Ax are open circuited and the wiper Wx is
connected to Bx resulting in only leakage currents being con-
sumed in the VR structure. In shutdown mode the VR latch
settings are maintained, so that, returning to operational mode
from power shutdown, the VR settings return to their previous
resistance values.
Ax
Wx
Bx
R
S
R
S
R
S
R
S
SHDN
D7
D6
D5
D4
D3
D2
D1
D0
RDAC
LATCH
&
DECODER
Figure 16. AD5204/AD5206 Equivalent RDAC Circuit
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the RDAC between Terminals A and
B are available with values of 10 k
, 50 k
and 100 k
. The
last digits of the part number determine the nominal resistance
value, e.g., 10 k
= 10; 100 k
= 100. The nominal resistance
(R
AB
) of the VR has 256 contact points accessed by the wiper
terminal, plus the B terminal contact. The eight-bit data word
in the RDAC latch is decoded to select one of the 256 possible
settings. The wiper’s first connection starts at the B terminal for
data 00
H
. This B terminal connection has a wiper contact resis-
tance of 45
. The second connection (10 k
part) is the first
tap point located at 84
[= R
BA
(nominal resistance)/256 + R
W
= 84
+ 45
] for data 01
H
. The third connection is the next
tap point representing 78 + 45 = 123
for data 02
H
. Each LSB
data value increase moves the wiper up the resistor ladder until
the last tap point is reached at 10006
. The wiper does not
directly connect to the A terminal. See Figure 16 for a simplified
diagram of the equivalent RDAC circuit.
The general transfer equation determining the digitally pro-
grammed output resistance between Wx and Bx is:
R
WB
(
Dx
) = (
Dx
)/256
×
R
BA
+
R
W
where
Dx
is the data contained in the 8-bit RDACx latch, and
R
BA
is the nominal end-to-end resistance.
For example, when V
B
= 0 V and A terminal is open-circuit, the
following output resistance values will be set for the following
RDAC latch codes (applies to the 10K potentiometer):
(1)
Table II.
D
(DEC)
R
WB
-
V
10006
5045
84
45
Output State
255
128
1
0
Full Scale
Midscale (
PR
= 0 Condition)
1 LSB
Zero Scale (Wiper Contact Resistance)
Note that in the zero-scale condition a finite wiper resistance of
45
is present. Care should be taken to limit the current flow
between W and B in this state to a maximum value of 20 mA to
avoid degradation or possible destruction of the internal switch
contact.
Like the mechanical potentiometer the RDAC replaces, it is
totally symmetrical. The resistance between the Wiper W and
Terminal A produces a digitally controlled resistance R
WA
.
When these terminals are used the B terminal should be tied to
the wiper. Setting the resistance value for R
WA
starts at a maxi-
mum value of resistance and decreases as the data loaded in the
latch is increased in value. The general transfer equation for this
operation is:
R
WA
(
Dx
) = (256–
Dx
)/256
×
R
BA
+
R
W
where
Dx
is the data contained in the 8-bit RDACx latch, and
R
BA
is the nominal end-to-end resistance. For example, when
V
A
= 0 V and B terminal is tied to the Wiper W the following
output resistance values will be set for the following RDAC
latch codes:
(2)
Table III.
D
(DEC)
R
WA
-
V
Output State
255
128
1
0
84
5045
10006
10045
Full Scale
Midscale (
PR
= 0 Condition)
1 LSB
Zero Scale
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