參數(shù)資料
型號： AD5204BR100
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字電位計
英文描述： SWITCH SLIDE DPDT RT ANG L=4MM
中文描述： QUAD 100K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO24
封裝： MS-013AD, SOIC-24
文件頁數(shù)： 2/11頁
文件大小： 173K
代理商： AD5204BR100
REV. 0
AD5204/AD5206–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
–2–
Parameter
Symbol
Conditions
Min
Typ
1
Max
Units
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
Resistor Differential NL
2
Resistor Nonlinearity Error
2
Nominal Resistor Tolerance
3
Resistance Temperature Coefficient
Nominal Resistance Match
Wiper Resistance
R-DNL
R-INL
R
AB
R
AB
/
T
R/R
AB
R
W
R
WB
, V
A
= No Connect
R
WB
, V
A
= No Connect
T
A
= +25
°
C
V
AB
= V
DD
, Wiper = No Connect
CH1 to 2, 3, 4, or 5, 6; V
AB
= V
DD
I
W
= 1 V/R, V
DD
= +5 V
–1
–2
–30
±
1/4
±
1/2
+1
+2
+30
LSB
LSB
%
ppm/
°
C
%
700
0.25
50
1.5
100
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs
Resolution
N
Differential Nonlinearity
4
DNL
Integral Nonlinearity
4
INL
Voltage Divider Temperature Coefficient
V
W
/
T
Full-Scale Error
V
WFSE
Zero-Scale Error
V
WZSE
RESISTOR TERMINALS
Voltage Range
5
V
A,
V
B,
V
W
Capacitance
6
Ax, Bx
C
A,
C
B
Capacitance
6
Wx
C
W
Shutdown Current
7
I
A_SD
Common-Mode Leakage
I
CM
DIGITAL INPUTS AND OUTPUTS
Input Logic High
V
IH
Input Logic Low
V
IL
Output Logic High
V
OH
Output Logic Low
V
OL
Input Current
I
IL
Input Capacitance
6
C
IL
POWER SUPPLIES
Power Single Supply Range
V
DD
Range
Power Dual Supply Range
V
DD/SS
Range
Positive Supply Current
I
DD
Negative Supply Current
I
SS
Power Dissipation
8
P
DISS
Power Supply Sensitivity
PSS
DYNAMIC CHARACTERISTICS
6, 9
Bandwidth –3 dB
BW_10K
BW_50K
BW_100K
Total Harmonic Distortion
THD
W
V
W
Settling Time (10K/50K/100K)
t
S
Resistor Noise Voltage
e
N_WB
INTERFACE TIMING CHARACTERISTICS Applies to All Parts
6, 10
Input Clock Pulsewidth
t
CH
, t
CL
Data Setup Time
t
DS
Data Hold Time
t
DH
CLK to SDO Propagation Delay
11
t
PD
CS
Setup Time
t
CSS
CS
High Pulsewidth
t
CSW
Reset Pulsewidth
t
RS
CLK Fall to
CS
Fall Setup
t
CSH0
CLK Fall to
CS
Rise Hold Time
t
CSH1
CS
Rise to Clock Rise Setup
t
CS1
NOTES
Typicals represent average readings at +25
°
C and V
= +5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-
tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 23 test circuit. I
W
= V
DD
/R
for both V
DD
= +3 V or V
= +5 V.
3
V
= V
) = No connect.
4
INL and DNL are measured at V
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
DNL specification limits of
±
1 LSB maximum are guaranteed monotonic operating conditions. See Figure 22 test circuit.
8
–1
–2
Bits
LSB
LSB
ppm/
°
C
LSB
LSB
±
1/4
±
1/2
15
–1
+1
+1
+2
Code = 40
H
Code = 7F
H
Code = 00
H
–2
0
0
+2
V
SS
V
DD
V
pF
pF
μ
A
nA
f = 1 MHz, Measured to GND, Code = 40
H
f = 1 MHz, Measured to GND, Code = 40
H
45
60
0.01
1
5
V
A
= V
B
= V
W
= 0, V
DD
= +2.7 V, V
SS
= –2.5 V
V
DD
= +5 V/+3 V
V
DD
= +5 V/+3 V
R
PULL–UP
= 1 k
to +5 V
I
OL
= 1.6 mA, V
LOGIC
= +5 V
V
IN
= 0 V or +5 V
2.4/2.1
V
V
V
V
μ
A
pF
0.8/0.6
4.9
0.4
±
1
5
V
SS
= 0 V
2.7
±
2.3
5.5
±
2.7
60
60
0.3
0.005
V
V
μ
A
μ
A
mW
%/%
V
IH
= +5 V or V
IL
= 0 V
V
SS
= –2.5 V, V
DD
= +2.7 V
V
IH
= +5 V or V
IL
= 0 V
V
DD
= +5 V
±
10%
12
12
0.0002
R
AB
= 10 k
R
AB
= 50 k
R
AB
= 100 k
V
A
= 1.414 V rms, V
B
= 0 V dc, f = 1 kHz
V
A
= 5 V, V
B
= 0 V,
±
1 LSB Error Band
R
WB
= 5 k
, f = 1 kHz,
PR
= 0
721
137
69
0.004
2/9/18
9
kHz
kHz
kHz
%
μ
s
nV/
√
Hz
Clock Level High or Low
20
5
5
1
15
40
90
0
0
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R
L
= 2 k
, C
L
< 20 pF
150
(V
DD
= +5 V
6
10% or +3 V
6
10%, V
SS
= 0 V, V
A
= +V
DD
, V
B
= 0 V, –40
8
C < T
A
< +85
8
C
unless otherwise noted.)
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