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參數(shù)資料
| 型號： | AD5171EVAL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD5171 |
| 標準包裝： | 1 |
| 主要目的： | 數(shù)字電位器 |
| 已用 IC / 零件： | AD5171 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD5171BRJZ5-R2DKR-ND - IC DGTL POT OTP 5K 12C SOT23-8 AD5171BRJZ50-R2DKR-ND - IC DGTL POT OTP 50K I2C SOT23-8 AD5171BRJZ10-R2DKR-ND - IC DGTL POT OTP 10K I2C SOT23-8 AD5171BRJZ100R2DKR-ND - IC DGTL POT OTP 100K I2C SOT23-8 AD5171BRJZ5-R7-ND - IC DGTL POT OTP 5K SOT23-8 AD5171BRJZ50-R7-ND - IC DGTL POT OTP 50K SOT23-8 AD5171BRJZ100-R7-ND - IC DGTL POT OTP 100K SOT23-8 AD5171BRJZ10-R7-ND - IC DGTL POT OTP 10K SOT23-8 AD5171BRJZ50-R2CT-ND - IC DGTL POT OTP 50K I2C SOT23-8 AD5171BRJZ5-R2CT-ND - IC DGTL POT OTP 5K 12C SOT23-8 更多... |
AD5171
Rev. D | Page 18 of 24
the instruction byte, the last byte in the write mode is the data
byte. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge bit).
The transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of SCL
(see Figure 35).
In read mode, the data byte follows immediately after the
acknowledgment of the slave address byte. Data is transmitted over
the serial bus in sequences of nine clock pulses (note the slight
difference from the write mode; there are eight data bits followed
by a no acknowledge bit). Similarly, the transitions on the SDA
line must occur during the low period of SCL and remain stable
during the high period of SCL (see Figure 37).
When all data bits are read or written, a stop condition is
established by the master. A stop condition is defined as a low-
to-high transition on the SDA line while SCL is high. In the
write mode, the master pulls the SDA line high during the 10th
clock pulse to establish a stop condition (see Figure 35 and
Figure 36). In the read mode, the master issues a no acknowledge
for the 9th clock pulse, that is, the SDA line remains high. The
master then brings the SDA line low before the 10th clock pulse,
which goes high to establish a stop condition (see Figure 37).
A repeated write function gives the user flexibility to update the
RDAC output a number of times, except after permanent
programming, addressing, and instructing the part only once.
During the write cycle, each data byte updates the RDAC output.
For example, after the RDAC has acknowledged its slave address
and instruction bytes, the RDAC output updates after these two
bytes. If another byte is written to the RDAC while it is still
addressed to a specific slave device with the same instruction,
this byte updates the output of the selected slave device. If
different instructions are needed, the write mode has to be
started with a new slave address, instruction, and data bytes.
Similarly, a repeated read function of the RDAC is also allowed.
CONTROLLING TWO DEVICES ON ONE BUS
Figure 38 shows two AD5171 devices on the same serial bus.
Each has a different slave address because the state of each AD0
pin is different, which allows each device to be independently
operated. The master device output bus line drivers are open-
drain pull-downs in a fully I2C-compatible interface.
MASTER
SDA SCL
AD0
AD5171
SDA SCL
AD0
AD5171
SDA
SCL
5V
Rp
5V
03
43
7-
0
38
Figure 38. Two AD5171 Devices on One Bus
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