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參數(shù)資料
| 型號： | AD5171BRJ50-R2 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | 64-Position OTP Digital Potentiometer |
| 中文描述： | 50K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO8 |
| 封裝： | MO-178-BA, SOT-23, 8 PIN |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 1722K |
| 代理商： | AD5171BRJ50-R2 |
AD5171
Parameter
DYNAMIC CHARACTERISTICS
6, 10, 11
Bandwidth –3 dB
Total Harmonic Distortion
Symbol
BW_5k
BW_10k
BW_50k
BW_100k
THD
Conditions
R
AB
= 5 k, Code = 0x20
R
AB
= 10 k, Code = 0x20
R
AB
= 50 k, Code = 0x20
R
AB
= 100 k, Code = 0x20
V
A
=1 V rms, R
AB
= 10 k,
V
B
= 0 V D
C
, f = 1 kHz
V
A
= 5 V ± 1 LSB error band,
V
B
= 0, measured at V
W
V
A
= 5 V ± 1 LSB error band,
V
B
= 0, measured at V
W
V
A
= 5 V ±1 LSB error band,
V
B
= 0, measured at V
W
R
AB
= 5 k, f = 1 kHz,
Code = 0x20
R
AB
= 10 k, f = 1 kHz,
Code = 0x20
Min
Typ
1
1500
600
110
60
0.05
Max
Unit
kHz
kHz
kHz
kHz
%
Adjustment Settling Time
t
S1
5
μs
OTP Settling Time
12
t
S_OTP
400
ms
Power-up Settling Time—Post Fuses Blown
t
S2
5
μs
Resistor Noise Voltage
e
N_WB
8
nV/√Hz
12
nV/√Hz
INTERFACE TIMING CHARACTERISTICS
(Applies to all parts
6,12
)
SCL Clock Frequency
t
BUF
Bus Free Time between Start and Stop
t
HD;STA
Hold Time (Repeated Start)
f
SCL
t
1
t
2
After this period, the first
clock pulse is generated
1.3
0.6
400
kHz
μs
μs
t
LOW
Low Period of SCL Clock
t
HIGH
High Period of SCL Clock
t
SU;STA
Setup Time for Start Condition
t
HD;DAT
Data Hold Time
t
SU;DAT
Data Setup Time
t
F
Fall Time of Both SDA and SCL Signals
t
R
Rise Time of Both SDA and SCL signals
t
SU;STO
Setup Time for Stop Condition
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
1.3
0.6
0.6
0.1
0.6
50
0.9
0.3
0.3
μs
μs
μs
μs
μs
μs
μs
μs
1
Typicals represent average readings at 25°C and V
DD
= 5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
V
AB
= V
DD
, Wiper (V
W
) = No connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output DAC. V
A
= V
DD
and V
B
= 0 V. DNL specification limits of
±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Different from operating power supply, power supply for OTP is used one-time only.
8
Different from operating current, supply current for OTP lasts approximately 400 ms for one-time needed only.
9
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
10
Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value result in the minimum overall power consumption.
11
All dynamic characteristics use V
DD
= 5 V.
12
Different from settling time after fuse is blown. The OTP settling time occurs once only.
SCL
SDA
t
1
t
2
t
3
t
8
t
8
t
9
t
4
t
5
t
9
t
7
t
6
t
10
P
P
S
0
Figure 3. Interface Timing Diagram
Rev. PrC | Page 4 of 20
Preliminary Technical Data
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD5171BRJ50-RL7 | 制造商:Rochester Electronics LLC 功能描述:6-BIT OTP I2C DIGITAL POT - Bulk 制造商:Analog Devices 功能描述: |
| AD5171BRJ5-R2 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD5171BRJ5-REEL7 | 制造商:Analog Devices 功能描述: |
| AD5171BRJ5-RL7 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD5171BRJZ100-R2 | 功能描述:IC DGTL POT OTP 100K I2C SOT23-8 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:- 標準包裝:3,000 系列:DPP 接片:32 電阻（歐姆）:10k 電路數(shù):1 溫度系數(shù):標準值 300 ppm/°C 存儲器類型:非易失 接口:3 線串行（芯片選擇，遞增，增/減） 電源電壓:2.5 V ~ 6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-WFDFN 裸露焊盤 供應商設備封裝:8-TDFN（2x3） 包裝:帶卷 (TR) |
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