參數(shù)資料
型號(hào)： AD5171BRJ10-RL7
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字電位計(jì)
英文描述： 64-Position OTP Digital Potentiometer
中文描述： 10K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO8
封裝： MO-178-BA, SOT-23, 8 PIN
文件頁(yè)數(shù)： 15/20頁(yè)
文件大?。?/td> 1722K
代理商： AD5171BRJ10-RL7
AD5171
Table 9. SDA Bits Definitions and Descriptions
Bit
Description
S
P
Stop Condition.
A
Acknowledge.
AD0
I
2
C Device Address Bit. Allows maximum of
two AD5171s to be addressed.
X
Don’t Care.
T
OTP Programming Bit. Logic 1 programs wiper
position permanently.
Bit
D5, D4, D3,
D2, D1, D0
E1, E0
0, 0
0, 1
1, 0
1, 1
Description
Data Bits.
Start Condition.
OTP Validation Bits.
Ready to Program.
Test Fuse Not Blown Successfully. (For Factory Setup Checking
Purpose Only. Users should not see these combinations).
Fatal Error. Try again.
Programmed Successfully. No further adjustments possible.
I
2
C Controller Programming
Write Bit Pattern Illustrations
SDA
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
INSTRUCTION BYTE
FRAME 1
DATA BYTE
SCL
ACK. BY
AD5171
ACK. BY
AD5171
ACK. BY
AD5171
STOP BY
MASTER
START BY
MASTER
0
1
1
0
1
1
0
AD0 R/W
0
X
X
X
X
X
X
X
X
X
D5
D4
D3
D2
D1
D0
9
1
9
1
9
0
Figure 36. Writing to the RDAC Register
SDA
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
INSTRUCTION BYTE
FRAME 1
DATA BYTE
SCL
ACK. BY
AD5171
ACK. BY
AD5171
ACK. BY
AD5171
STOP BY
MASTER
START BY
MASTER
0
1
1
0
1
1
0
AD0 R/W
1
X
X
X
X
X
X
X
X
X
D5
D4
D3
D2
D1
D0
9
1
9
1
9
0
Figure 37. Activating One-Time Programming
Read Bit Pattern Illustration
SDA
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
RDAC REGISTER
SCL
ACK. BY
AD5171
NO ACK. BY
MASTER
STOP BY
MASTER
START BY
MASTER
0
1
1
0
1
1
0
AD0
E1
E0
D5
D4
D3
D2
D1
D0
9
1
9
R/W
0
Figure 38. Reading Data from RDAC Register
For users who prefer to use external controllers, the AD5171
can be controlled via an I
2
C compatible serial bus and is
connected to this bus as slave device. Referring to Figure 36,
Figure 37, and Figure 38, the 2-wire I
2
C serial bus protocol
operates as follows:
1.
The master initiates data transfer by establishing a start
condition, which is when SDA from high-to-low while SCL
is high (Figure 36 and Figure 37). The following byte is the
slave address byte, which consists of the 6 MSBs as a slave
address defined as 010110. The next bit is AD0, which is an
I
2
C device address bit. Depending on the states of their
AD0 bits, two AD5171 can be addressed on the same bus
(Figure 39). The last LSB is the R/W bit, which determines
whether data will be read from or written to the slave
device.
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line goes low during
the 9
th
clock pulse (this is termed the Acknowledge bit). At
Rev. PrC | Page 15 of 20
Preliminary Technical Data
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