
AD5171
For log taper adjustment, such as volume control, Figure 45
shows another way of resistance scaling to achieve the log taper
function. In this circuit, the smaller the R2 with respect to R
AB
,
the more like the pseudo log taper characteristic it behaves. The
wiper voltage is simply
I
WB
R
WA
R
WB
R
+
W
V
R
R
D
V
×
=
2
||
)
||
(
)
(
(6)
V
I
R1
B
A
R2
V
O
W
0
Figure 45. Resistor Scaling with Log Adjustment Characteristics
RESOLUTION ENHANCEMENT
The resolution can be doubled in the potentiometer mode of
operation by using three digital potentiometers. Borrowed from
ADI’s patented RDAC segmentation technique, users can con-
figure three AD5171 (Figure 46) to double the resolution. First,
U
3
must be parallel with a discrete resistor R
P
, which is chosen
to be equal to a step resistance (R
P
= R
AB
/64). One can see that
adjusting U1 and U2 together forms the coarse 6-bit adjustment
and that adjusting U3 alone forms the finer 6-bit adjustment. As a
result, the effective resolution becomes 12-bit.
U1
A1
B1
W1
U2
A2
B2
W3
W2
U3
A3
B3
R
P
COARSE
ADJUSTMENT
FINE
ADJUSTMENT
0
Figure 46. Doubling the Resolution
RDAC CIRCUIT SIMULATION MODEL
The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the digital potentio-
meters. Configured as a potentiometer divider, the –3 dB
bandwidth of the AD5171 (5 k
resistor) measures 1.5 MHz at
half scale. Figure 14 to Figure 17 provide the large signal BODE
plot characteristics of the four available resistor versions 5 k
10 k
, 50 k
, and 100 k
. A parasitic simulation model is
shown in Figure 47. Listing 1 provides a macro model net list
for the 10 k
device.
55pF
C
25pF
C
25pF
A
B
RDAC
10k
W
C
W
0
Figure 47. Circuit Simulation Model for RDAC = 10 k
Listing 1. Macro Model Net List for RDAC
.PARAM D=64, RDAC=10E3
*
.SUBCKT DPOT (A,W,B)
*
CA A
RWA
A
CW W
RWB W
CB
B
0
W
0
B
0
25E-12
{(1-D/64)*RDAC+60}
55E-12
{D/64*RDAC+60}
25E-12
*
.ENDS DPOT
Rev. PrC | Page 18 of 20
Preliminary Technical Data