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參數(shù)資料
| 型號(hào)： | AD5170BRM100-RL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字電位計(jì) |
| 英文描述： | 256-Position Two-Time Programmable I2C Digital Potentiometer |
| 中文描述： | 100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO10 |
| 封裝： | 3 X 4.90 MM, MO-187BA, MSOP-10 |
| 文件頁數(shù)： | 14/24頁 |
| 文件大?。?/td> | 900K |
| 代理商： | AD5170BRM100-RL7 |
AD5170
ESD PROTECTION
All digital inputs—SDA, SCL, AD0, and AD1—are protected
with a series input resistor and parallel Zener ESD structures, as
shown in Figure 34 and Figure 35.
Rev. A | Page 14 of 24
LOGIC
340
GND
0
Figure 34. ESD Protection of Digital Pins
A, B, W
GND
0
Figure 35. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5170 V
DD
to GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer opera-
tion. Supply signals present on Terminal A, Terminal B, and
Terminal W that exceed V
DD
or GND will be clamped by the
internal forward-biased diodes (see Figure 36).
GND
A
W
B
V
DD
0
Figure 36. Maximum Terminal Voltages Set by V
DD
and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at Terminal A, Terminal B, and Terminal W (see Figure 36), it is
important to power V
DD
/GND before applying any voltage to
Terminal A, Terminal B, and Terminal W. Otherwise, the diode
will be forward biased such that V
DD
is powered unintentionally
and may affect the rest of the user’s circuit. The ideal power-up
sequence is GND, V
DD
, the digital inputs, and then V
A
/V
B
/V
W
.
The relative order of powering V
A
, V
B
, V
W
, and the digital
inputs is not important as long as they are powered after
V
DD
/GND.
POWER SUPPLY CONSIDERATIONS
To minimize the package pin count, both the one-time pro-
gramming and normal operating voltage supplies share the
same V
DD
terminal of the AD5170. The AD5170 employs fuse
link technology that requires 5.25 V to 5.5 V for blowing the
internal fuses to achieve a given setting, but normal V
DD
can be
anywhere between 2.7 V and 5.5 V after the fuse programming
process. As a result, dual voltage supplies and isolation are
needed if system V
DD
is lower than the required V
DD_OTP
. The
fuse programming supply (either an on-board regulator or
rack-mount power supply) must be rated at 5.25 V to 5.5 V and
able to provide a 100 mA current for 400 ms for successful one-
time programming. Once fuse programming is completed, the
V
DD_OTP
supply must be removed to allow normal operation at
2.7 V to 5.5 V and the device will consume current in
μ
A range.
Figure 37 shows the simplest implementation of a dual supply
requirement by using a jumper. This approach saves one voltage
supply, but draws additional current and requires manual
configuration.
V
DD
5.5V
R1
50k
R2
C1
10
μ
F
C2
1nF
250k
CONNECT J1 HERE
FOR OTP
CONNECT J1 HERE
AFTER OTP
AD5170
0
Figure 37. Power Supply Requirement
An alternate approach in 3.5 V to 5.25 V systems adds a signal
diode between the system supply and the OTP supply for
isolation, as shown in Figure 38.
V
DD
3.5V–5.25V
5.5V
D1
C1
1
μ
F
C2
1nF
APPLY FOR OTP ONLY
AD5170
0
Figure 38. Isolate 5.5 V OTP Supply from 3.5 V to 5.25 V Normal Operating
Supply. The V
DD_OTP
must be removed once OTP is completed.
V
DD
2.7V
5.5V
P1
P1=P2=FDV302P, NDS0610
R1
10k
P2
C1
10
μ
F
C2
1nF
APPLY FOR OTP ONLY
AD5170
0
Figure 39. Isolate 5.5 V OTP Supply from 2.7 V Normal Operating Supply.
The V
DD_OTP
supply must be removed once OTP is completed.
For users who operate their systems at 2.7 V, use of the
bidirectional low threshold P-Ch MOSFETs is recommended
for the supply’s isolation. As shown in Figure 39, this assumes
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