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參數(shù)資料
| 型號： | AD5161BRM5 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/20頁 |
| 文件大小： | 0K |
| 描述： | IC POT DGTL 5K 256POS 10-MSOP |
| 標準包裝： | 50 |
| 接片： | 256 |
| 電阻（歐姆）： | 5k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標準值 45 ppm/°C |
| 存儲器類型： | 易失 |
| 接口： | I²C，SPI |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 10-MSOP |
| 包裝： | 管件 |
AD5161
Data Sheet
Rev. B | Page 18 of 20
LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE
While most legacy systems may be operated at one voltage, a
new component may be optimized at another. When two systems
operate the same signal at two different voltages, proper level
shifting is needed. For instance, one can use a 3.3 V E2PROM to
interface with a 5 V digital potentiometer. A level shifting scheme is
needed to enable a bidirectional communication so that the setting
of the digital potentiometer can be stored to and retrieved from
and M2 can be any N-channel signal FETs, or if VDD falls below
2.5 V, low threshold FETs such as the FDV301N.
E2PROM
AD5161
SDA1
SCL1
D
G
RP
3.3V
5V
S
M1
SCL2
SDA2
RP
G
S
M2
VDD1 = 3.3V
VDD2 = 5V
D
Figure 45. Level Shifting for Operation at Different Potentials
ESD PROTECTION
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures shown in Figure 46 and Figure 47.
This applies to the digital input pins SDI/SDA, CLK/SCL, and
CS/AD0.
LOGIC
340
Vss
Figure 46. ESD Protection of Digital Pins
A,B,W
VSS
Figure 47. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5161 VDD and GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer
operation. Supply signals present on terminals A, B, and W that
exceed VDD or GND will be clamped by the internal forward
biased diodes (see Figure 48).
A
VDD
B
W
VSS
Figure 48. Maximum Terminal Voltages Set by VDD and VSS
POWER-UP SEQUENCE
Since the ESD protection diodes limit the voltage compliance at
terminals A, B, and W (see Figure 48), it is important to power
VDD/GND before applying any voltage to terminals A, B, and W;
otherwise, the diode will be forward biased such that VDD will
be powered unintentionally and may affect the rest of the user’s
circuit. The ideal power-up sequence is in the following order:
GND, VDD, digital inputs, and then VA/B/W. The relative order of
powering VA, VB, VW, and the digital inputs is not important as
long as they are powered after VDD/GND.
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum lead length
layout design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with disc or chip ceramic
capacitors of 0.01 F to 0.1 F. Low ESR 1 F to 10 F tantalum
or electrolytic capacitors should also be applied at the supplies
to minimize any transient disturbance and low frequency ripple
(see Figure 49). Note that the digital ground should also be
joined remotely to the analog ground at one point to minimize
the ground bounce.
AD5161
VDD
C1
C3
GND
10
F
0.1
F
+
VDD
Figure 49. Power Supply Bypassing
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| AD5161BRMZ10 | 制造商:Analog Devices 功能描述:IC 8-BIT DIGITAL POT |
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