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參數資料
| 型號： | AD5161BRM5 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字電位計 |
| 英文描述： | 256-Position SPI/I2C Selectable Digital Potentiometer |
| 中文描述： | 5K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO10 |
| 封裝： | 3 X 4.90 MM, M0-187BA, MSOP-10 |
| 文件頁數： | 17/20頁 |
| 文件大小： | 1002K |
| 代理商： | AD5161BRM5 |
AD5161
LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE
While most legacy systems may be operated at one voltage, a
new component may be optimized at another. When two
systems operate the same signal at two different voltages, proper
level shifting is needed. For instance, one can use a 3.3 V
E
2
PROM to interface with a 5 V digital potentiometer. A level
shifting scheme is needed to enable a bidirectional
communication so that the setting of the digital potentiometer
can be stored to and retrieved from the E
2
PROM. Figure 44
shows one of the implementations. M1 and M2 can be any
N-channel signal FETs, or if V
DD
falls below 2.5 V, low threshold
FETs such as the FDV301N.
Rev. 0 | Page 17 of 20
E
2
PROM
AD5161
SDA1
SCL1
D
G
R
P
R
P
3.3V
5V
S
M1
SCL2
SDA2
R
P
R
P
G
S
M2
V
DD1
= 3.3V
V
DD2=
5V
D
Figure 44. Level Shifting for Operation at Different Potentials
ESD PROTECTION
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures shown in Figure 45 and Figure 46.
This applies to the digital input pins SDI/SDA, CLK/SCL, and
CS/AD0.
LOGIC
340
Vss
Figure 45. ESD Protection of Digital Pins
A,B,W
V
SS
Figure 46. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5161 V
DD
and GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer
operation. Supply signals present on terminals A, B, and W that
exceed V
DD
or GND will be clamped by the internal forward
biased diodes (see Figure 47).
A
V
DD
B
W
V
SS
Figure 47. Maximum Terminal Voltages Set by V
DD
and V
SS
POWER-UP SEQUENCE
Since the ESD protection diodes limit the voltage compliance at
terminals A, B, and W (see Figure 47), it is important to power
V
DD
/GND before applying any voltage to terminals A, B, and W;
otherwise, the diode will be forward biased such that V
DD
will be
powered unintentionally and may affect the rest of the user’s
circuit. The ideal power-up sequence is in the following order:
GND, V
DD
, digital inputs, and then V
A/B/W
. The relative order of
powering V
A
, V
B
, V
W
, and the digital inputs is not important as
long as they are powered after V
DD
/GND.
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum lead length
layout design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to the
device should be bypassed with disc or chip ceramic capacitors
of 0.01 μF to 0.1 μF. Low ESR 1 μF to 10 μF tantalum or
electrolytic capacitors should also be applied at the supplies to
minimize any transient disturbance and low frequency ripple
(see Figure 48). Note that the digital ground should also be
joined remotely to the analog ground at one point to minimize
the ground bounce.
AD5161
V
DD
C1
C3
GND
10
μ
F
0.1
μ
F
+
V
DD
Figure 48. Power Supply Bypassing
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