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參數(shù)資料
| 型號： | AD5161BRM50 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | 256-Position SPI/I2C Selectable Digital Potentiometer |
| 中文描述： | 50K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO10 |
| 封裝： | 3 X 4.90 MM, M0-187BA, MSOP-10 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 1002K |
| 代理商： | AD5161BRM50 |
AD5161
TIMING CHARACTERISTICS—5 k, 10 k, 50 k, 100 k VERSIONS
(V
DD
= +5V ± 10%, or +3V ± 10%; V
A
= V
DD
; V
B
= 0 V; –40°C < T
A
< +125°C; unless otherwise noted.)
Table 3.
Parameter
Symbol
SPI INTERFACE TIMING CHARACTERISTICS
6, 10
(Specifications Apply to All Parts)
Clock Frequency
f
CLK
Input Clock Pulsewidth
t
CH
, t
CL
Data Setup Time
t
DS
Data Hold Time
t
DH
CS Setup Time
t
CSS
CS High Pulsewidth
t
CSW
CLK Fall to CS Fall Hold Time
t
CSH0
CLK Fall to CS Rise Hold Time
t
CSH1
CS Rise to Clock Rise Setup
t
CS1
I
2
C INTERFACE TIMING CHARACTERISTICS
6, 11
(Specifications Apply to All Parts)
SCL Clock Frequency
f
SCL
t
BUF
Bus Free Time between STOP and START
t
1
t
HD;STA
Hold Time (Repeated START)
t
2
Conditions
Min
Typ
1
Max
25
400
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
kHz
μs
μs
Clock level high or low
20
5
5
15
40
0
0
10
1.3
0.6
After this period, the first clock pulse is
generated.
t
LOW
Low Period of SCL Clock
t
HIGH
High Period of SCL Clock
t
SU;STA
Setup Time for Repeated START Condition
t
HD;DAT
Data Hold Time
t
SU;DAT
Data Setup Time
t
F
Fall Time of Both SDA and SCL Signals
t
R
Rise Time of Both SDA and SCL Signals
t
SU;STO
Setup Time for STOP Condition
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
1.3
0.6
0.6
100
0.6
50
0.9
300
300
μs
μs
μs
μs
ns
ns
ns
μs
NOTES
1
Typical specifications represent average readings at +25°C and V
DD
= 5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
V
AB
= V
DD
, Wiper (V
W
) = no connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = V
DD
and V
B
= 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
9
All dynamic characteristics use V
DD
= 5 V.
10
See timing diagram for location of measured values. All input control voltages are specified with t
R
= t
F
= 2 ns (10% to 90% of 3 V) and timed from a voltage
level of 1.5 V.
11
See timing diagrams for locations of measured values.
Rev. 0 | Page 5 of 20
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