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參數(shù)資料
| 型號(hào)： | AD5160 |
| 廠商： | Analog Devices, Inc. |
| 元件分類(lèi)： | 數(shù)字電位計(jì) |
| 英文描述： | 256-Position SPI Compatible Digital Potentiometer |
| 中文描述： | 256位SPI兼容數(shù)字電位器 |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大?。?/td> | 847K |
| 代理商： | AD5160 |
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AD5160
TIMING CHARACTERISTICS—5 k, 10 k, 50 k, 100 k VERSIONS
(V
DD
= +5V ± 10%, or +3V ± 10%; V
A
= V
DD
; V
B
= 0 V; –40°C < T
A
< +125°C; unless otherwise noted.)
Table 3.
Parameter
Symbol
Conditions
SPI INTERFACE TIMING CHARACTERISTICS
6, 10
(Specifications Apply to All Parts)
Clock Frequency
f
CLK
Input Clock Pulsewidth
t
CH
, t
CL
Clock level high or low
Data Setup Time
t
DS
Data Hold Time
t
DH
CS Setup Time
t
CSS
CS High Pulsewidth
t
CSW
CLK Fall to CS Fall Hold Time
t
CSH0
CLK Fall to CS Rise Hold Time
t
CSH1
CS Rise to Clock Rise Setup
t
CS1
Min
Typ
1
Max
25
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
20
5
5
15
40
0
0
10
NOTES
1
Typical specifications represent average readings at +25°C and V
DD
= 5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
V
AB
= V
DD
, Wiper (V
W
) = no connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = V
DD
and V
B
= 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
9
All dynamic characteristics use V
DD
= 5 V.
10
See timing diagram for location of measured values. All input control voltages are specified with t
R
= t
F
= 2 ns (10% to 90% of 3 V) and timed from a voltage
level of 1.5 V.
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= +25°C, unless otherwise noted.)
Table 4.
Parameter
V
DD
to GND
V
A
, V
B
, V
W
to GND
I
MAX1
Digital Inputs and Output Voltage to GND
Operating Temperature Range
Maximum Junction Temperature (T
JMAX
)
Storage Temperature
Lead Temperature (Soldering, 10 sec)
Thermal Resistance
2
θ
JA
: MSOP-10
NOTES
1
Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2
Package power dissipation = (T
JMAX
– T
A
)/θ
JA
.
Value
–0.3 V to +7 V
V
DD
±20 mA
0 V to +7 V
–40°C to +125°C
150°C
–65°C to +150°C
300°C
230°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 5 of 16
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