參數(shù)資料
型號: AD5100EVAL
廠商: Analog Devices, Inc.
英文描述: System-Management IC with Programmable Quad Voltage Monitoring and Supervisory Functions
中文描述: 系統(tǒng)管理IC與可編程四路電壓監(jiān)測和監(jiān)督職能
文件頁數(shù): 5/32頁
文件大?。?/td> 495K
代理商: AD5100EVAL
Preliminary Technical Data
AD5100
Parameter
Sleep Mode Supply Current
Active Mode Supply Current
Rev. PrJ | Page 5 of 32
Symbol
I
SLEEP_V1MON
I
POWER_V1MON
Conditions
V
2MON
= 0 V
V
2MON
= 12 V
V
2MON
Edge Triggered Mode
Selected
Min
Typ
1
Max
10
3
3
Unit
μA
mA
mA
Device Power On Threshold
Device Power Up V2MON Minimum
Pulse Width (Figure 14)
Device Power Down Delay
OTP Supply Voltage
6
OTP Supply Current
OTP Settling Time
7
TIMING CHARACTERISTICS
8
Parameter Adjustment Time
I2C Interface Timing
Characteristics
SCL Clock Frequency
t
BUF
Bus Free Time between Start
and Stop
t
HD;STA
Hold Time after (Repeated)
START condition. After this period,
the first clock is generated
t
LOW
Low Period of SCL Clock
t
HIGH
High Period of SCL Clock
t
SU;STA
Setup Time for Start
Condition
t
HD;DAT
Data Hold Time
t
SU;DAT
Data Setup Time
t
F
Fall Time of Both SDA and SCL
Signals
t
R
Rise Time of Both SDA and SCL
Signals
t
SU;STO
Setup Time for Stop
Condition
Notes:
1.
Represent typical values at 25°C, V
1MON
= 12 V, and V
2MON
= 12 V.
2.
Does not apply if V
2MON
is a digital signal.
3.
The
RESET
short-circuit current is the maximum pullup current when
RESET
is driven low by a μP bidirectional reset pin.
4.
It is typical for the SCL and SDA have resistors to be pulled up to V
3MON
. However, care must be taken to ensure that the minimum V
IH
is met when the SCL and SDA are driven directly from a low voltage
logic controller without pull-up resistors.
5.
Initial V
2MON
ON minimum remains as 2.2V but the -0.3V to 30V specifications apply afterwards.
6.
V
OTP
can be furnished by Factory 6V power supply, rather than on-board power supply, when performing factory programming. A 10uF tantalum capacitor is required on V
OTP
during operation regardless
of whether the OTP fuses are programmed.
7.
The OTP settling time occurs only once if OTP function is used.
8.
Guaranteed by design and not subject to production test.
t
8
t
9
t
6
V2MON,IH
V2MON,IL
2.2
0.4
V
V
t
V2MON_PW
V
OTP
I
VOTP
t
S_OTP
V2MON < 0.4V (Normal Mode)
I2C Initiated Power Down
For OTP only
For OTP only
4
6
200
2
10
12
6.5
ms
s
μs
V
mA
ms
t
S1
1
μs
f
SCL
t
1
1.3
400
KHz
μs
t
2
0.6
μs
t
3
t
4
t
5
1.3
0.6
0.6
50
μs
μs
μs
t
6
t
7
t
8
0.1
0.9
0.3
μs
μs
μs
t
9
0.3
μs
t
10
0.6
μs
0
t
1
t
2
t
3
t
8
t
9
t
4
t
7
t
5
t
2
t
10
P
S
S
SCL
SDA
P
Figure 2. Digital Interface Timing Diagram
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