- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄8962 > AD5064BRUZ (Analog Devices Inc)IC DAC 16BIT 4CH BUF OUT 16TSSOP PDF資料下載
參數(shù)資料
| 型號： | AD5064BRUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/28頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT 4CH BUF OUT 16TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | nanoDAC™ |
| 設(shè)置時間： | 8µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 30mW |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 4 電壓，雙極 |
| 采樣率（每秒）： | 125k |
| 產(chǎn)品目錄頁面： | 781 (CN2011-ZH PDF) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁當(dāng)前第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
Data Sheet
AD5024/AD5044/AD5064
Rev. F | Page 25 of 28
MICROPROCESSOR INTERFACING
AD5024/AD5044/AD5064/AD5064-1 to Blackfin ADSP-
BF53x Interface
Figure 52 shows a serial interface between the AD5024/AD5044/
AD5064/AD5064-1 and the Blackfin ADSP-BF53x microproces-
sor. The ADSP-BF53x processor family incorporates two dual-
channel synchronous serial ports, SPORT1 and SPORT0, for
serial and multiprocessor communications. Using SPORT0 to
connect to the AD5024/AD5044/AD5064/AD5064-1, the setup
for the interface is as follows: DT0PRI drives the DIN pin of the
AD5024/AD5044/AD5064/AD5064-1, and TSCLK0 drives the
SCLK of the parts. The SYNC pin is driven from TFS0.
AD5024/
AD5044/
AD5064/
AD5064-1*
ADSP-BF53x*
*ADDITIONAL PINS OMITTED FOR CLARITY.
SYNC
TFS0
DIN
DT0PRI
SCLK
TSCLK0
06803-
012
Figure 52. AD5024/AD5044/AD5064/AD5064-1 to Blackfin ADSP-BF53x
Interface
AD5024/AD5044/AD5064/AD5064-1 to 68HC11/68L11
Interface
Figure 53 shows a serial interface between the AD5024/AD5044/
AD5064/AD5064-1 and the 68HC11/68L11 microcontroller.
SCK of the 68HC11/68L11 drives the SCLK of the AD5024/
AD5044/AD5064/AD5064-1, and the MOSI output drives the
serial data line of the DAC.
AD5024/
AD5044/
AD5064/
AD5064-1*
68HC11/68L11*
*ADDITIONAL PINS OMITTED FOR CLARITY.
SYNC
PC7
SCLK
SCK
DIN
MOSI
06803-
013
Figure 53. AD5024/AD5044/AD5064/AD5064-1 to 68HC11/68L11 Interface
The SYNC signal is derived from a port line (PC7). The setup
conditions for correct operation of this interface are as follows:
The 68HC11/68L11 is configured with its CPOL bit as 0, and its
CPHA bit as 1. When data is being transmitted to the DAC, the
SYNC line is taken low (PC7). When the 68HC11/68L11 is
configured as described previously, data appearing on the MOSI
output is valid on the falling edge of SCK. Serial data from the
68HC11/68L11 is transmitted in 8-bit bytes with only eight
falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. To load data to the AD5024/AD5044/
AD5064, PC7 is left low after the first eight bits are transferred,
and a second serial write operation is performed to the DAC.
PC7 is taken high at the end of this procedure.
AD5024/AD5044/AD5064/AD5064-1 to 80C51/80L51
Interface
Figure 54 shows a serial interface between the AD5024/AD5044/
AD5064/AD5064-1 and the 80C51/80L51 microcontroller. The
setup for the interface is as follows: TxD of the 80C51/80L51
drives SCLK of the AD5024/AD5044/AD5064/AD5064-1, and
RxD drives the serial data line of the part. The SYNC signal is
again derived from a bit-programmable pin on the port. In this
case, Port Line P3.3 is used. When data is to be transmitted to the
AD5024/AD5044/AD5064/AD5064-1, P3.3 is taken low. The
80C51/80L51 transmit data in 8-bit bytes only; thus, only eight
falling clock edges occur in the transmit cycle. To load data to
the DAC, P3.3 is left low after the first eight bits are transmitted,
and a second write cycle is initiated to transmit the second byte of
data. P3.3 is taken high following the completion of this cycle.
The 80C51/80L51 output the serial data in a format that has the
LSB first. The AD5024/AD5044/AD5064/AD5064-1 must
receive data with the MSB first. The 80C51/80L51 transmit
routine should take this into account.
AD5024/
AD5044/
AD5064/
AD5064-1*
*ADDITIONAL PINS OMITTED FOR CLARITY.
DIN
RxD
SYNC
P3.3
80C51/80L51*
SCLK
TxD
06803-
014
Figure 54. AD5024/AD5044/AD5064/AD5064-1 to 80C512/80L51 Interface
AD5024/AD5044/AD5064/AD5064-1 to MICROWIRE
Interface
Figure 55 shows an interface between the AD5024/AD5044/
AD5064/AD5064-1 and any MICROWIRE-compatible device.
Serial data is shifted out on the falling edge of the serial clock and is
clocked into the AD5024/AD5044/AD5064/AD5064-1 on the
rising edge of the SCLK.
AD5024/
AD5044/
AD5064/
AD5064-1*
*ADDITIONAL PINS OMITTED FOR CLARITY.
SCLK
SO
SYNC
CS
MICROWIRE*
DIN
SK
06803-
015
Figure 55. AD5024/AD5044/AD5064/AD5064-1 to MICROWIRE Interface
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VE-J0L-MZ-F4 | CONVERTER MOD DC/DC 28V 25W |
| ICS8705BYILFT | IC CLOCK GENERATOR ZD 32-LQFP |
| DAC8221FPZ | IC DAC 12BIT DUAL W/BUFF 24DIP |
| VI-2NF-MW-F3 | CONVERTER MOD DC/DC 72V 100W |
| VE-J0B-MZ-F1 | CONVERTER MOD DC/DC 95V 25W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD5064BRUZ-1 | 功能描述:IC DAC 16BIT 4CH BUF OUT 14TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:nanoDAC™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
| AD5064BRUZ-1REEL7 | 功能描述:IC DAC 16BIT 4CH BUF OUT 14TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:nanoDAC™ 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD5064BRUZ-REEL7 | 功能描述:IC DAC 16BIT 4CH BUF OUT 16TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:nanoDAC™ 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD5065 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Fully Accurate, 12-/14-/16-Bit, Dual, VOUT nanoDAC SPI Interface, 4.5 V to 5.5 V in a TSSOP |
| AD50651 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Fully Accurate, 16-Bit, Unbuffered VOUT, Quad SPI Interface, 2.7 V to 5.5 V nanoDAC in a TSSOP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。