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參數(shù)資料
| 型號： | AD5063BRMZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT 2.7-5.5V 10MSOP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1,000 |
| 系列： | nanoDAC™ |
| 設(shè)置時間： | 4µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 333k |
AD5063
Rev. C | Page 15 of
20
AD5063 to 68HC11/68L11 Interface
Figure 32 shows a serial interface between the AD5063 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the SCLK pin of the AD5063, and the MOSI output
drives the serial data line of the DAC. The SYNC signal is
derived from a port line (PC7). The setup conditions for correct
operation of this interface require that the 68HC11/68L11 be
configured so that its CPOL bit is 0 and its CPHA bit is 1. When
data is being transmitted to the DAC, the SYNC line is taken
low (PC7). When the 68HC11/68L11 are configured with their
CPOL bit set to 0 and their CPHA bit set to 1, data appearing
on the MOSI output is valid on the falling edge of SCK. Serial
data from the 68HC11/68L11 is transmitted in 8-bit bytes with
only eight falling clock edges occurring in the transmit cycle.
Data is transmitted MSB first. To load data to the AD5063, PC7
is left low after the first eight bits are transferred, and then a
second serial write operation is performed to the DAC, with
PC7 taken high at the end of this procedure.
AD50631
1ADDITIONAL PINS OMITTED FOR CLARITY
PC7
SCK
MOSI
SYNC
SCLK
DIN
04
76
6-
03
2
68HC11/
68L111
Figure 32. AD5063 to 68HC11/68L11 Interface
AD5063 to Blackfin ADSP-BF53x Interface
Figure 33 shows a serial interface between the AD5063 and
the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x
processor family incorporates two dual-channel synchronous
serial ports, SPORT1 and SPORT0, for serial and multiprocessor
communications. Using SPORT0 to connect to the AD5063, the
setup for the interface is as follows: DT0PRI drives the DIN pin
of the AD5063, TSCLK0 drives the SCLK of the part, and TFS0
drives SYNC.
ADSP-BF53x1
AD50631
1ADDITIONAL PINS OMITTED FOR CLARITY
DT0PRI
TSCLK0
TFS0
DIN
SCLK
SYNC
04
76
6-
03
3
Figure 33. AD5063 to Blackfin ADSP-BF53x Interface
AD5063 to 80C51/80L51 Interface
Figure 34 shows a serial interface between the AD5063 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows: TxD of the 80C51/80L51 drives SCLK of the AD5063,
and RxD drives the serial data line of the part. The SYNC signal
is again derived from a bit-programmable pin on the port. In
this case, Port Line P3.3 is used. When data is to be transmitted
to the AD5063, P3.3 is taken low. The 80C51/80L51 transmits
data only in 8-bit bytes; therefore, only eight falling clock edges
occur in the transmit cycle. To load data to the DAC, P3.3 is left
low after the first eight bits are transmitted, and a second write
cycle is initiated to transmit the second byte of data. P3.3 is taken
high following the completion of this cycle. The 80C51/80L51
output the serial data in a format that has the LSB first. The
AD5063 requires its data with the MSB as the first bit received.
The 80C51/80L51 transmit routine should take this into
account.
80C51/80L511
AD50631
1ADDITIONAL PINS OMITTED FOR CLARITY
P3.3
TxD
RxD
SYNC
SCLK
DIN
04
76
6-
03
4
Figure 34. AD5063 to 80C51/80L51 Interface
AD5063 to MICROWIRE Interface
Figure 35 shows an interface between the AD5063 and any
MICROWIRE-compatible device. Serial data is shifted out on
the falling edge of the serial clock and clocked into the AD5063
on the rising edge of the SK.
MICROWIRE1
AD50631
1ADDITIONAL PINS OMITTED FOR CLARITY
CS
SK
SO
SYNC
SCLK
DIN
04
76
6-
03
5
Figure 35. AD5063 to MICROWIRE Interface
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