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參數(shù)資料
| 型號(hào)： | AD5062BRJZ-1500RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 8/20頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT 2.7-5.5V SOT23-8 |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | nanoDAC™ |
| 設(shè)置時(shí)間： | 4µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-8 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類(lèi)型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 1.3M |
| 其它名稱(chēng)： | AD5062BRJZ-1500RL7DKR |
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AD5062
Rev. A | Page 16 of 20
AD5062 to 68HC11/68L11 Interface
Figure 38 shows a serial interface between the AD5062 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the SCLK pin of the AD5062, while the MOSI output
drives the serial data line of the DAC. The SYNC signal is
derived from a port line (PC7). The setup conditions for correct
operation of this interface require that the 68HC11/68L11 be
configured so that its CPOL bit is 0 and its CPHA bit is 1. When
data is being transmitted to the DAC, the SYNC line is taken
low (PC7). When the 68HC11/68L11 is configured where its
CPOL bit is 0 and its CPHA bit is 1, data appearing on the
MOSI output is valid on the falling edge of SCK. Serial data
from the 68HC11/68L11 is transmitted in 8-bit bytes with only
eight falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. In order to load data to the AD5062,
PC7 is left low after the first eight bits are transferred, and a
second serial write operation is performed to the DAC, and PC7
is taken high at the end of this procedure.
AD50621
1ADDITIONAL PINS OMITTED FOR CLARITY
PC7
SCK
MOSI
SYNC
SCLK
DIN
04766-032
68HC11/
68L111
Figure 38. AD5062 to 68HC11/68L11 Interface
AD5062 to Blackfin ADSP-BF53x Interface
Figure 39 shows a serial interface between the AD5062 and the
Blackfin ADSP-53x microprocessor. The ADSP-BF53x proces-
sor family incorporates two dual-channel synchronous serial
ports, SPORT1 and SPORT0, for serial and multiprocessor
communications. Using SPORT0 to connect to the AD5062,
the setup for the interface is: DT0PRI drives the SDIN pin of
the AD5062, while TSCLK0 drives the SCLK of the part; the
SYNC is driven from TFS0.
ADSP-BF53x1
AD50621
1ADDITIONAL PINS OMITTED FOR CLARITY
DT0PRI
TSCLK0
TFS0
DIN
SCLK
SYNC
04766-033
Figure 39. AD5062 to Blackfin ADSP-BF53x Interface
AD5062 to 80C51/80L51 Interface
Figure 40 shows a serial interface between the AD5062 and the
80C51/80L51 microcontroller. The setup for the interface is:
TxD of the 80C51/80L51 drives SCLK of the AD5062 while
RxD drives the serial data line of the part. The SYNC signal is
again derived from a bit-programmable pin on the port. In this
case, Port Line P3.3 is used. When data is to be transmitted to
the AD5062, P3.3 is taken low. The 80C51/80L51 transmits data
only in 8-bit bytes; thus only eight falling clock edges occur in
the transmit cycle. To load data to the DAC, P3.3 is left low after
the first eight bits are transmitted, and a second write cycle is
initiated to transmit the second byte of data. P3.3 is taken high
following the completion of this cycle. The 80C51/80L51
outputs the serial data in a format that has the LSB first. The
AD5062 requires its data with the MSB as the first bit received;
the 80C51/80L51 transmit routine should take this into account.
80C51/80L511
AD50621
1ADDITIONAL PINS OMITTED FOR CLARITY
P3.3
TxD
RxD
SYNC
SCLK
DIN
04766-034
Figure 40. AD5062 to 80C51/80L51 Interface
AD5062 to MICROWIRE Interface
Figure 41 shows an interface between the AD5062 and any
MICROWIRE-compatible device. Serial data is shifted out on
the falling edge of the serial clock and is clocked into the
AD5062 on the rising edge of the SK.
MICROWIRE1
AD50621
1ADDITIONAL PINS OMITTED FOR CLARITY
CS
SK
SO
SYNC
SCLK
DIN
04766-035
Figure 41. AD5062 to MICROWIRE Interface
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