參數(shù)資料
型號: AD5062BRJ-2
廠商: ANALOG DEVICES INC
元件分類: DAC
英文描述: Full Accurate 16 Bit Vout nanoDac, 2.7V- 5.5V, in a Sot 23
中文描述: SERIAL INPUT LOADING, 3 us SETTLING TIME, 16-BIT DAC, PDSO8
封裝: SOT-23, 8 PIN
文件頁數(shù): 4/17頁
文件大小: 833K
代理商: AD5062BRJ-2
AD5062/AD5063
Preliminary Technical Data
TIMING CHARACTERISTICS
(VDD = 2.7-5.5 V; all specifications TMIN to TMAX unless otherwise noted)
Parameter
Limit
1
t
1
33
t
2
13
t
3
12
t
4
13
t
5
5
t
6
4.5
t
7
0
t
8
33
t
9
13
Rev. Pr B | Page 4 of 17
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC
to SCLK Falling Edge Setup Time
Data Setup Time
Data Hold Time
SCLK Falling Edge to
SYNC
Rising Edge
Minimum
SYNC
High Time
SYNC
Rising Edge to next SCLK Fall
Ignore
3
.
NOTES
1All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2See Figure 1.
3Maximum SCLK frequency is 30 MHz.
Specifications subject to change without notice.
Figure 1. Timing Diagram
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