AD5025/AD5045/AD5065
Rev. 0 | Page 12 of 28
CH1 5V
CH2 500mV
M2s
A CH2
1.2V
2
1
T 55%
CH1 = SCLK
CH2 = VOUT
VDD = 5V
POWER-UP TO MIDSCALE
0
68
44
-0
41
Figure 24. Exiting Power-Down to Midscale
6
3
1
–1
–3
0
2.5
5.0
7.5
10.0
G
L
IT
C
H
A
M
PL
IT
U
D
E
(
m
V)
TIME (μs)
5
4
2
–2
0
06
84
4-
0
42
Figure 25. Digital-to-Analog Glitch Impulse
7
4
1
–1
–4
0
2.5
5.0
7.5
10.0
G
L
IT
CH
AM
P
L
IT
UDE
(
m
V
)
TIME (μs)
5
6
3
2
0
–2
–3
VDD = 5V, VREF = 4.096V
TA = 25C
0
68
44
-0
43
Figure 26. Analog Crosstalk
7
4
1
–1
–4
0
2.5
5.0
7.5
10.0
G
L
IT
CH
AM
P
L
IT
UDE
(
m
V
)
TIME (μs)
5
6
3
2
0
–2
–3
VDD = 5V, VREF = 4.096V
TA = 25°C
06
84
4-
0
44
Figure 27. DAC-to-DAC Crosstalk
4s/DIV
1μ
V/
D
IV
VDD = 5V, VREF = 4.096V
TA = 25C
DAC LOADED WITH MIDSCALE
06
84
4-
0
45
Figure 28. 0.1 Hz to 10 Hz Output Noise Plot
0
–20
–50
–80
–100
5
10
30
40
55
V
OU
T
L
E
VEL
(d
B
)
FREQUENCY (kHz)
–90
–70
–60
–10
–30
–40
20
50
VDD = 5V,
TA = 25C
DAC LOADED WITH MIDSCALE
VREF = 3.0V ± 200mV p-p
06
84
4-
0
46
Figure 29. Total Harmonic Distortion