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參數(shù)資料
| 型號： | AD2S93BP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 位置變換器 |
| 英文描述： | Aluminum Electrolytic Capacitor; Capacitor Type:Industrial Grade; Voltage Rating:150VDC; Capacitor Dielectric Material:Aluminum Electrolytic; Operating Temperature Range:-40 C to +85 C; Capacitance:16uF RoHS Compliant: Yes |
| 中文描述： | LVDT OR RVDT TO DIGITAL CONVERTER, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大小： | 349K |
| 代理商： | AD2S93BP |
AD2S93
REV. A
–3–
Parameter
Test Conditions
Min
Typ
Max
Units
SERIAL CLOCK (SCLK)
SCK Input Rate
Maximum Read Rate (16 Bits)
2
9.2
MHz
μ
s
Continuous
POWER SUPPLY
I
DD
I
SS
5
5
7
7
10
10
mA
mA
NOTES
1
The signal input voltage maximum should always be set at 10% less than the reference input.
2
Nominal + FS = V
A–B
= V
REF
/2, FS = –V
A–B
= V
REF
/2
3
With G = 10; Sensitivity 34.2
μ
V pk/LSB
4
Phase shift cause gain errors. “See Phase Shift and Quadrative Effects.”
Specifications subject to change without notice.
SCLK
DATA
CS
t
*
t
3
t
4
t
1
t
5
t
7
LSB
MSB
t * = THE MINIMUM ACCESS TIME: USER DEPENDENT
TOTAL MAX READ TIME =
t
2
+ 16. (
t
3
+
t
4
) +
t
7
TOTAL MAX READ TIME = 600 +16 (250 + 250) + 150 ns
TOTAL MAX READ TIME = 600 + 8000 + 150 ns
TOTAL MAX READ TIME = 8.750 μs (SINGLE READ ONLY)
t
2
t
6
Timing Diagram
Parameter
AD2S93
Units
Test Conditions
t
1
t
2
t
3
t
4
t
5
t
6
t
7
1
150
600
250
250
100
600
150
ns max
ns min
ns min
ns min
ns max
ns min
ns max
CS
to DATA Enable
CS
to 1st SCLK Positive Edge
SCLK High Pulse
SCLK Low Pulse
SCLK Positive Edge to DATA Valid
CS
High Pulse Width
CS
High to DATA High Z (Bus Relinquish)
NOTE
1
SCLK can only be applied after t
2
has elapsed.
TIMING CHARACTERISTICS
(V
DD
= +5 V
±
5%, AGND = DGND = 0 V, T
A
= –40
°
C to +85
°
C unless otherwise noted)
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