參數(shù)資料
型號： AD2S90
廠商： Analog Devices, Inc.
英文描述： Low Cost, Complete 12-Bit Resolver-to-Digital Converter
中文描述： 低成本，完整的12位分解到數(shù)字轉(zhuǎn)換器
文件頁數(shù)： 4/12頁
文件大?。?/td> 168K
代理商： AD2S90
AD2S90
REV. D
–4–
RECOMMENDED OPERATING CONDITIONS
Power Supply Voltage (V
DD
– V
SS
) . . . . . . . . . .
±
5 V dc
±
5%
Analog Input Voltage (SIN, COS & REF) . . . . .2 V rms
±
10%
Signal and Reference Harmonic Distortion . . . . . . . . . . . . 10%
Phase Shift between Signal and Reference . . . . . . . . . . . . .
±
10
°
Ambient Operating Temperature Range
Industrial (AP) . . . . . . . . . . . . . . . . . . . . . . .–40
°
C to +85
°
C
ABSOLUTE MAXIMUM RATINGS*
V
DD
to AGND . . . . . . . . . . . . . . . . . . . .–0.3 V dc to +7.0 V dc
V
SS
to AGND . . . . . . . . . . . . . . . . . . . .+0.3 V dc to –7.0 V dc
AGND to DGND . . . . . . . . . . . . –0.3 V dc to V
DD
+ 0.3 V dc
Analog Inputs to AGND
REF . . . . . . . . . . . . . . . . . .V
SS
– 0.3 V dc to V
DD
+ 0.3 V dc
SIN, SIN LO . . . . . . . . . . . V
SS
– 0.3 V dc to V
DD
+ 0.3 V dc
COS, COS LO . . . . . . . . . . V
SS
– 0.3 V dc to V
DD
+ 0.3 V dc
Analog Output to AGND
VEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
SS
to V
DD
Digital Inputs to DGND, CSB,
SCLK, RES . . . . . . . . . . . . . . . –0.3 V dc to V
DD
+ 0.3 V dc
Digital Outputs to DGND, NM, A, B,
DIR, CLKOUT DATA . . . . . . –0.3 V dc to V
DD
+ 0.3 V dc
Operating Temperature Range
Industrial (AP) . . . . . . . . . . . . . . . . . . . . . . .–40
°
C to +85
°
C
Storage Temperature Range . . . . . . . . . . . . . –65
°
C to +150
°
C
Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . . 300
°
C
Power Dissipation to +75
°
C . . . . . . . . . . . . . . . . . . . . 300 mW
Derates above +75
°
C by . . . . . . . . . . . . . . . . . . . . . 10 mW/
°
C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model
Temperature Range Accuracy
Package Option
AD2S90AP –40
°
C to +85
°
C
10.6 arc min P-20A
CAUTION
The AD2S90 features an input protection circuit consisting of large “distributed” diodes and
polysilicon series resistors to dissipate both high energy discharges (Human Body Model) and
fast, low energy pulses (Charges Device Model).
Proper ESD precautions are strongly recommended to avoid functional damage or performance
degradation. For further information on ESD precautions, refer to Analog Devices
ESD
Prevention Manual
.
PIN DESCRIPTIONS
Pin
No. Mnemonic Function
1
2
AGND
SIN
Analog ground, reference ground.
SIN channel noninverting input connect to
resolver SIN HI output. SIN to SIN LO =
2 V rms
±
10%.
SIN channel inverting input connect to
resolver SIN LO.
Serial interface data output. High impedance
with
CS
= HI. Enabled by
CS
= 0.
Serial interface clock. Data is clocked out on
“first” negative edge of SCLK after a LO transi-
tion on
CS
. 12 SCLK pulses to clock data out.
Chip select. Active LO. Logic LO transition
enables DATA output.
Encoder A output.
Encoder B output.
Encoder North Marker emulation output.
Pulse triggered as code passes through zero.
Three common pulsewidths available.
Indicates direction of rotation of input.
Logic HI = increasing angular rotation.
Logic LO = decreasing angular rotation.
Digital power ground return.
Negative power supply, –5 V dc
±
5%.
Positive power supply, +5 V dc
±
5%.
Positive power supply, +5 V dc
±
5%. Must
be connected to Pin 13.
North marker width control. Internally pulled
HI via 50 k
nominal.
Internal VCO clock output. Indicates angular
velocity of input signals. Max nominal rate =
1.536 MHz. CLKOUT is a 300 ns positive pulse.
Indicates angular velocity of input signals.
Positive voltage w.r.t. AGND indicates in-
creasing angle. FSD = 375 rps.
Converter reference input. Normally derived
from resolver primary excitation. REF = 2 V
rms nominal. Phase shift w.r.t. COS and SIN
=
±
10
°
max
COS channel inverting input. Connect to
resolver COS LO.
COS channel noninverting input. Connect to
resolver COS HI output. COS = 2 V rms
±
10%.
3
SIN LO
4
DATA
5
SCLK
6
CS
7
8
9
A
B
NM
10
DIR
11
12
13
14
DGND
V
SS
V
DD
V
DD
15
NMC
16
CLKOUT
17
VEL
18
REF
19
COS LO
20
COS
3 2 1 20 19
9 10 11 12 13
18
17
16
15
14
4
5
6
7
8
TOP VIEW
(Not to Scale)
PIN 1
DATA
SCLK
CS
A
B
REF
VEL
CLKOUT
NMC
V
DD
AD2S90
S
S
A
C
C
N
D
D
V
S
V
D
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATION
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