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參數(shù)資料
| 型號(hào)： | AD2S83IPZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 3/19頁(yè) |
| 文件大小： | 0K |
| 描述： | IC CONV R/D MONO VAR RES 44PLCC |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 類型： | R/D 轉(zhuǎn)換器 |
| 輸入類型： | 并聯(lián) |
| 輸出類型： | 數(shù)字 |
| 接口： | 并聯(lián) |
| 電流 - 電源： | 30mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 帶卷 (TR) |
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AD2S83
–11–
REV. E
DIRECTION Output
The DIRECTION (DIR) output indicates the direction of the
input rotation. Any change in the state of DIR precedes the
corresponding BUSY, DATA and RIPPLE CLOCK updates.
DIR can be considered as an asynchronous output and can
make multiple changes in state between two consecutive LSB
update cycles. This occurs when the direction of rotation of the
input changes but the magnitude of the rotation is less than 1 LSB.
COMPLEMENT
The
COMPLEMENT input is an active low input and is inter-
nally pulled to +VS via 100 k
.
Strobing
DATA LOAD and COMPLEMENT pins to logic LO
will set the logic HI bits of the AD2S83 counter to a LO state.
Those bits of the applied data which are logic LO will not
change the corresponding bits in the AD2S83 counter.
For Example:
Initial Counter State
1 0 1 0 1
Applied Data Word
1 1 0 0 0
Counter State after
DATA LOAD
1 1 0 0 0
Initial Counter State
1 0 1 0 1
Applied Data Word
1 1 0 0 0
Counter State after
DATA LOAD and Complement
0 0 1 0 1
In order to read the counter following a
DATA LOAD, the
procedure below should be followed:
1. Place outputs in high impedance state (
ENABLE = HI).
2. Present data to pins.
3. Pull
DATA LOAD and COMPLEMENT pins to ground.
4. Wait 100 ns.
5. Remove data from pins.
6. Remove outputs from high impedance state (
ENABLE =
LO).
7. Read outputs.
CIRCUIT FUNCTIONS AND DYNAMIC PERFORMANCE
The AD2S83 allows the user great flexibility in choosing the
dynamic characteristics of the resolver-to-digital conversion to
ensure the optimum system performance. The characteristics
are set by the external components shown in Figure 1. The
Component Selection section explains how to select desired
maximum tracking rate and bandwidth values. The following
paragraphs explain in greater detail the circuit of the AD2S83
and the variations in the dynamic performance available to the
user.
Loop Compensation
The AD2S83 (connected as shown in Figure 1) operates as a
Type 2 tracking servo loop where the VCO/counter combination
and Integrator perform the two integration functions inherent in
a Type 2 loop.
Additional compensation in the form of a pole/zero pair is
required to stabilize the loop.
This compensation is implemented by the integrator compo-
nents (R4, C4, R5, C5).
The overall response the converter is that of a unity gain second
order low-pass filter, with the angle of the resolver as the input
and the digital position data as the output.
The AD2S83 does not have to be connected as tracking con-
verter, parts of the circuit can be used independently. This is
particularly true of the Ratio Multiplier which can be used as a
control transformer. (For more information contact Motion
Control Applications.)
A block diagram of the AD2S83 is given in Figure 4.
RATIO
MULTIPLIER
VCO
PHASE
SENSITIVE
DEMODULATOR
AC ERROR
A, SIN ( – ) SIN
t
SIN
t
COS
SIN
t
DIGITAL
CLOCK
DIRECTION
R4
R5
R6
C5
C4
VELOCITY
INTEGRATOR
Figure 4. Functional Diagram
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