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參數(shù)資料
| 型號(hào)： | AD2S83IP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 位置變換器 |
| 英文描述： | Variable Resolution, Resolver-to-Digital Converter |
| 中文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 3/19頁 |
| 文件大?。?/td> | 176K |
| 代理商： | AD2S83IP |
AD2S83
Typ
Parameter
Conditions
Min
Max
Units
COMPLEMENT
Internally Pulled High via 100 k
to +V
S
. Logic LO to Activate;
No Connect for Normal Operation
DATA LOAD
Sense
Internally Pulled High via 100 k
to +V
. Logic LO Allows
Data to be Loaded into the
Counters from the Data Lines
150
300
ns
BUSY
6, 7
Sense
Width
Load
Logic HI When Position O/P Changing
150
350
1
ns
LSTTL
Use Additional Pull-Up (See Figure 2)
DIRECTION
6
Sense
Logic HI Counting Up
Logic LO Counting Down
Max Load
3
LSTTL
RIPPLE CLOCK
6
Sense
Logic HI
All 1s to All 0s
All 0s to All 1s
Dependent on Input Velocity
Before Next Busy
Width
Reset
Load
300
ns
3
LSTTL
DIGITAL INPUTS
Input High Voltage, V
IH
INHIBIT
,
ENABLE
DB1–DB16, Byte Select
±
V
S
=
±
11.4 V, V
L
= 5.0 V
INHIBIT
,
ENABLE
DB1–DB16, Byte Select
±
V
S
=
±
12.6 V, V
L
= 5.0 V
2.0
V
Input Low Voltage, V
IL
0.8
V
DIGITAL INPUTS
Input High Current, I
IH
INHIBIT
,
ENABLE
DB1–DB16
±
V
=
±
12.6 V, V
= 5.5 V
INHIBIT
,
ENABLE
DB1–DB16, Byte Select
±
V
S
=
±
12.6 V, V
L
= 5.5 V
6
100
μ
A
Input Low Current, I
IL
6
100
μ
A
DIGITAL INPUTS
Low Voltage, V
IL
ENABLE
= HI
SC1, SC2,
DATA LOAD
±
V
=
±
12.0 V, V
L
= 5.0 V
ENABLE
= HI
SC1, SC2,
DATA LOAD
±
V
S
=
±
12.0 V, V
L
= 5.0 V
1.0
V
Low Current, I
IL
–400
μ
A
DIGITAL OUTPUTS
High Voltage, V
OH
DB1–DB16
RIPPLE CLK, DIR
±
V
S
=
±
12.0 V, V
L
= 4.5 V
I
= 100
μ
A
DB1–DB16
RIPPLE CLK, DIR
±
V
S
=
±
12.0 V, V
L
= 5.5 V
I
OL
= 1.2 mA
2.4
V
Low Voltage, V
OL
0.4
V
NOTES
1
Angular accuracy is not guaranteed <50 Hz reference frequency.
2
Linearity derates from 500 kHz–1000 kHz @ 0.0017%/kHz.
3
Refer to Definition of Linearity, “The AD2S83 as a Silicon Tachogenerator.”
4
Worst case reversion error at temperature extremes.
5
Velocity output offset dependent on value for R6.
6
Refer to timing diagram.
7
Busy pulse guaranteed up to a VCO rate of 900 kHz.
All min and max specifications are guaranteed. Specifications in
boldface
are tested on all production units at final electrical test.
Specifications subject to change without notice.
AD2S83
–3–
REV. D
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