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| 型號： | AD2S80ALD |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 位置變換器 |
| 英文描述： | Variable Resolution, Monolithic Resolver-to-Digital Converter |
| 中文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDIP40 |
| 封裝： | SIDE BRAZED, CERAMIC, DIP-40 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大小： | 268K |
| 代理商： | AD2S80ALD |
AD2S80A
REV. A
–7–
CONVE RT E R OPE RAT ION
When connected in a circuit such as shown in Figure 1 the
AD2S80A operates as a tracking resolver-to-digital converter
and forms a T ype 2 closed-loop system. T he output will auto-
matically follow the input for speeds up to the selected maxi-
mum tracking rate. No convert command is necessary as the
conversion is automatically initiated by each LSB increment, or
decrement, of the input. Each LSB change of the converter ini-
tiates a BUSY pulse.
T he AD2S80A is remarkably tolerant of input amplitude and
frequency variation because the conversion depends only on the
ratio of the input signals. Consequently there is no need for ac-
curate, stable oscillator to produce the reference signal. T he in-
clusion of the phase sensitive detector in the conversion loop
ensures a high immunity to signals that are not coherent or are
in quadrature with the reference signal.
SIGNAL CONDIT IONING
T he amplitude of the SINE and COSINE signal inputs should
be maintained within 10% of the nominal values if full perfor-
mance is required from the velocity signal.
T he digital position output is relatively insensitive to amplitude
variation. Increasing the input signal levels by more than 10%
will result in a loss in accuracy due to internal overload. Reduc-
ing levels will result in a steady decline in accuracy. With the
signal levels at 50% of the correct value, the angular error will
increase to an amount equivalent to 1.3 LSB. At this level the
repeatability will also degrade to 2 LSB and the dynamic re-
sponse will also change, since the dynamic characteristics are
proportional to the signal level.
T he AD2S80A will not be damaged if the signal inputs are
applied to the converter without the power supplies and/or the
reference.
RE FE RE NCE INPUT
T he amplitude of the reference signal applied to the converter’s
input is not critical, but care should be taken to ensure it is kept
within the recommended operating limits.
T he AD2S80A will not be damaged if the reference is supplied
to the converter without the power supplies and/or the signal
inputs.
HARMONIC DIST ORT ION
T he amount of harmonic distortion allowable on the signal and
reference lines is 10%.
Square waveforms can be used but the input levels should be
adjusted so that the average value is 1.9 V rms. (For example, a
square wave should be 1.9 V peak.) T riangular and sawtooth
waveforms should have a amplitude of 2 V rms.
Note: T he figure specified of 10% harmonic distortion is for
calibration convenience only.
POSIT ION OUT PUT
T he resolver shaft position is represented at the converter out-
put by a natural binary parallel digital word. As the digital posi-
tion output of the converter passes through the major carries,
i.e., all “1s” to all “0s” or the converse, a RIPPLE CLOCK
(RC) logic output is initiated indicating that a revolution or a
pitch of the input has been completed.
T he direction of input rotation is indicated by the DIRECT ION
(DIR) logic output. T his direction data is always valid in ad-
vance of a RIPPLE CLOCK pulse and, as it is internally
latched, only changing state (1 LSB min change) with a corre-
sponding change in direction.
Both the RIPPLE CLOCK pulse and the DIRECT ION data
are unaffected by the application of the
INHIBIT
. T he static
positional accuracy quoted is the worst case error that can occur
over the full operating temperature excluding the effects of off-
set signals at the INT EGRAT OR INPUT (which can be
trimmed out—see Figure 1), and with the following conditions:
input signal amplitudes are within 10% of the nominal; phase
shift between signal and reference is less than 10 degrees.
T hese operating conditions are selected primarily to establish a
repeatable acceptance test procedure which can be traced to na-
tional standards. In practice, the AD2S80A can be used well
outside these operating conditions providing the above points
are observed.
VE LOCIT Y SIGNAL
T he tracking converter technique generates an internal signal at
the output of the integrator (the INT EGRAT OR OUT PUT
pin) that is proportional to the rate of change of the input angle.
T his is a dc analog output referred to as the VELOCIT Y signal.
In many applications it is possible to use the velocity signal of
the AD2S80A to replace a conventional tachogenerator.
DC E RROR SIGNAL
T he signal at the output of the phase sensitive detector (DE-
MODULAT OR OUT PUT ) is the signal to be nulled by the
tracking loop and is, therefore, proportional to the error be-
tween the input angle and the output digital angle. T his is the
dc error of the converter; and as the converter is a T ype 2 servo
loop, it will increase if the output fails to track the input for any
reason. It is an indication that the input has exceeded the maxi-
mum tracking rate of the converter or, due to some internal
malfunction, the converter is unable to reach a null. By connect-
ing two external comparators, this voltage can be used as a
“built-in-test.”
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| AD2S80ASD | 功能描述:IC R/D CONV TRACKING 40CDIP RoHS:否 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
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| AD2S80ASE/883B | 制造商:Rochester Electronics LLC 功能描述:40 PIN PLCC 8 ARC MIN 883 - Bulk |
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