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參數(shù)資料
| 型號： | AD2S80AJD |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 位置變換器 |
| 英文描述： | Variable Resolution, Monolithic Resolver-to-Digital Converter |
| 中文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CDIP40 |
| 封裝： | SIDE BRAZED, CERAMIC, DIP-40 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 268K |
| 代理商： | AD2S80AJD |
AD2S80A
REV. A
–10–
CIRCUIT FUNCT IONS AND DY NAMIC PE RFORMANCE
T he AD2S80A allows the user greater flexibility in choosing the
dynamic characteristics of the resolver-to-digital conversion to
ensure the optimum system performance. T he characteristics
are set by the external components shown in Figure 1, and the
section “COMPONENT SELECT ION” explains how to select
desired maximum tracking rate and bandwidth values. T he fol-
lowing paragraphs explain in greater detail the circuit of the
AD2S80A and the variations in the dynamic performance avail-
able to the user.
Loop Compensation
T he AD2S80A (connected as shown in Figure 1) operates as a
T ype 2 tracking servo loop where the VCO/counter combination
and Integrator perform the two integration functions inherent in
a T ype 2 loop.
Additional compensation in the form of a pole/zero pair is re-
quired to stabilize any T ype 2 loop to avoid the loop gain char-
acteristic crossing the 0 dB axis with 180
°
of additional phase
lag, as shown in Figure 5.
T his compensation is implemented by the integrator compo-
nents (R4, C4, R5, C5).
T he overall response of such a system is that of a unity gain sec-
ond order low pass filter, with the angle of the resolver as the in-
put and the digital position data as the output.
T he AD2S80A does not have to be connected as tracking con-
verter, parts of the circuit can be used independently. T his is
particularly true of the Ratio Multiplier which can be used as a
control transformer (see Application Note).
A block diagram of the AD2S80A is given in Figure 3.
Ratio Multiplier
T he ratio multiplier is the input section of the AD2S80A and
compares the signal from the resolver input angle,
θ
, to the
digital angle,
φ
, held in the counter. Any difference between
these two angles results in an analog voltage at the AC ERROR
OUT PUT . T his circuit function has historically been called
a “Control T ransformer” as it was originally performed by an
electromechanical device known by that name.
T he AC ERROR signal is given by
A
1
sin (
θ
–
φ
) sin
ω
t
where
ω
= 2
π
f
REF
f
REF
= reference frequency
A1, the gain of the ratio multiplier stage is 14.5.
So for 2 V rms inputs signals
AC ERROR output in volts/(bit of error)
=
2
×
sin
360
n
×
A
1
where n = bits per rev
= 1,024 for 10 bits resolution
= 4,096 for 12 bits
= 16,384 for 14 bits
= 65,536 for 16 bits
giving an AC ERROR output
= 178 mV/bit @ 10 bits resolution
= 44.5 mV/bit @ 12 bits
= 11.125 mV/bit @ 14 bits
= 2.78 mV/bit @ 16 bits
T he ratio multiplier will work in exactly the same way whether
the AD2S80A is connected as a tracking converter or as a con-
trol transformer, where data is preset into the counters using the
DAT A LOAD pin.
HF Filter
T he AC ERROR OUT PUT may be fed to the PSD via a simple
ac coupling network (R2, C1) to remove any dc offset at this
point. Note, however, that the PSD of the AD2S80A is a
wideband demodulator and is capable of aliasing HF noise
down to within the loop bandwidth. T his is most likely to hap-
pen where the resolver is situated in particularly noisy environ-
ments, and the user is advised to fit a simple HF filter R1, C2
prior to the phase sensitive demodulator.
T he attenuation and frequency response of a filter will affect the
loop gain and must be taken into account in deriving the loop
transfer function. T he suggested filter (R1, C1, R2, C2) is
shown in Figure 1 and gives an attenuation at the reference
frequency (f
REF
) of 3 times at the input to the phase sensitive
demodulator .
Values of components used in the filter must be chosen to en-
sure that the phase shift at f
REF
is within the allowable signal to
reference phase shift of the converter.
Phase Sensitive Demodulator
T he phase sensitive demodulator is effectively ideal and devel-
ops a mean dc output at the DEMODULAT OR OUT PUT
pin of
±
2 2
π
×
(
DEMODULATOR INPUT rmsvoltage
)
Figure 3. Functional Diagram
PHASE
SENSITIVE
DEMODULATOR
A
1
sin (
θ
–
φ
) sin
ω
t
AC ERROR
sin
θ
sin
ω
t
cos
θ
sin
ω
t
DIGITAL
φ
VCO
R5
R6
C5
C4
R4
INTEGRATOR
VELOCITY
RATIO
MULTIPLIER
CLOCK
DIRECTION
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