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參數(shù)資料
| 型號(hào)： | AD2S1210CSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/36頁 |
| 文件大小： | 0K |
| 描述： | IC CONV R/D VAR RES OSC 48-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | R/D 轉(zhuǎn)換器 |
| 分辨率（位）： | 10，12，14，16 b |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 電壓電源： | 模擬和數(shù)字 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 配用： | EVAL-AD2S1210EDZ-ND - BOARD EVAL AD2S1210 |
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AD2S1210
Rev. A | Page 24 of 36
DIGITAL INTERFACE
The angular position and angular velocity are represented by
binary data and can be extracted either via a 16-bit parallel
interface or via a 4-wire serial interface that operates at clock
rates of up to 25 MHz. The AD2S1210 programmable functions
are controlled using a set of on-chip registers. Data is written to
these registers using either the serial or the parallel interface.
SOE INPUT
The serial output enable pin, SOE, is held high to enable the
parallel interface. The SOE pin is held low to enable the serial
interface, which places Pin DB0 to Pin DB12 in the high imped-
ance state. Pin DB13 is the serial clock input (SCLK), Pin DB14
is the serial data input (SDI), Pin DB15 is the serial data output
(SDO), and WR/FSYNC is the frame synchronization input.
SAMPLE INPUT
The AD2S1210 operates on a Type II tracking closed-loop
principle. The loop continually tracks the position and velocity
of the resolver without the need for external conversion and
wait states. The position and velocity registers are external to
the loop and are updated with a high-to-low transition of the
SAMPLE signal. This pin must be held low for at least t16 ns
to guarantee correct latching of the data.
DATA FORMAT
The digital angle data represents the absolute position of the
resolver shaft as a 10-bit to 16-bit unsigned binary word. The
digital velocity data is a 10-bit to 16-bit twos complement word,
which represents the velocity of the resolver shaft rotating in
either a clockwise or a counterclockwise direction.
PARALLEL INTERFACE
The parallel interface is selected holding the SOE pin high. The
chip select pin, CS, must be held low to enable the interface.
Writing to the AD2S1210
The on-chip registers of the AD2S1210 are written to, in parallel
mode, using an 8-bit parallel interface, D7 to D0, and the WR/
FSYNC pin. The MSB of each 8-bit word written to the AD2S1210
indicates whether the 8-bit word is a register address or data.
The MSB (D7) of each register address defined on the AD2S1210
is high (see the
section). The MSB of each data
word written to the AD2S1210 is low. To write to one of the
registers, the user must first place the AD2S1210 into configura-
tion mode using the A0 and A1 inputs. Then the 8-bit address
should be written to the AD2S1210 using Pin DB7 to Pin DB0,
and latched using the rising edge of the
WR/FSYNC input. The
data can then be presented on Pin DB7 to Pin DB0 and again
latched into the part using the WR/FSYNC input.
shows
the timing specifications to follow when writng to the configura-
tion registers. Note that the
RD input should be held high when
writing to the AD2S1210.
Reading from the AD2S1210
The following data can be read back from the AD2S1210:
Angular position
Angular velocity
Fault register data
Status of on-chip registers
The angular position and angular velocity data can be read back
in either normal mode or configuration mode. To read the
status of the fault register or the remaining on-chip registers,
the part must be put into configuration mode.
Reading from the AD2S1210 in Configuration Mode
To read back data stored in one of the on-chip registers, including
the fault register, the user must first place the AD2S1210 into
configuration mode using the A0 and A1 inputs. The 8-bit address
of the register to be read should then be written to the part, as
described in the Writing to the AD2S1210 section. This transfers
the relevant data to the output register. The data can then be
read using the RD input as described previously. When reading
back data from any of the read/write registers (see
), the
8-bit word consists of the seven bits of data in the relevant register,
D6 to D0, and an error bit, D7. If the error bit is returned high,
this indicates that the data read back from the device does not
match the configuration data written to the device in the previous
write cycle.
If the user wants to read back the angular position or velocity
data while in configuration mode, a falling edge of the SAMPLE
input is required to update the information in the position and
velocity registers. The data in these registers can then be read back
by addressing the required register and reading back the data as
described previously.
shows the timing specifications to
follow when reading from the configuration registers.
Reading from the AD2S1210 in Normal Mode
To read back position or velocity data from the AD2S1210, the
information stored in the position and velocity registers should
first be updated using the SAMPLE input. A high-to-low transition
on the SAMPLE input transfers the data from the position and
velocity integrators to the position and velocity registers. The
fault register is also updated on the high-to-low transition of the
SAMPLE input. The status of the A0 and A1 inputs determines
whether the position or velocity data is transferred to the output
register. The CS pin must be held low to transfer the selected
data to the output register. Finally, the RD input is used to read
the data from the output register and to enable the output buffer.
The output buffer is enabled when CS and RD are held low. The
data pins return to a high impedance state when RD returns to
a high state. If the user is reading data continuously, RD can be
reapplied a minimum of t20 ns after it was released.
The timing requirements for the read cycle are shown in Figure 30.
Note that the WR/FSYNC input should be high when RD is low.
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| AD2S1210DSTZ | 功能描述:IC CONV R/D VAR RES OSC 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 類型:數(shù)據(jù)采集系統(tǒng)（DAS） 分辨率（位）:16 b 采樣率（每秒）:21.94k 數(shù)據(jù)接口:MICROWIRE?，QSPI?，串行，SPI? 電壓電源:模擬和數(shù)字 電源電壓:1.8 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（6x6） 包裝:托盤 |
| AD2S1210DSTZ | 制造商:Analog Devices 功能描述:IC, ADC, 16BIT, PARALLEL, SERIAL, LQFP-4 |
| AD2S1210SST-EP-RL7 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC IC 10-16 Bit R/D Cnvtr w/Ref Oscilltr RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風(fēng)格: 封裝 / 箱體: |
| AD2S1210SSTZ-EPRL7 | 功能描述:IC CONV R/D VAR REF OSC 48LQFP 制造商:analog devices inc. 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:500 |
| AD2S1210WDSTZ | 制造商:Analog Devices 功能描述: |
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