AVDD = DVDD" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� AD2S1210BSTZ
寤犲晢锛� Analog Devices Inc
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 33/36闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC CONV R/D 10-16BIT 48-LQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1
椤炲瀷锛� R/D 杞�(zhu菐n)鎻涘櫒
鍒嗚鲸鐜囷紙浣嶏級锛� 10锛�12锛�14锛�16 b
鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� 涓茶锛屽苟鑱�(li谩n)
闆诲闆绘簮锛� 妯℃摤鍜屾暩(sh霉)瀛�
闆绘簮闆诲锛� 4.75 V ~ 5.25 V
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 48-LQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 48-LQFP锛�7x7锛�
鍖呰锛� 鎵樼洡
鐢�(ch菐n)鍝佺洰閷勯爜(y猫)闈細 790 (CN2011-ZH PDF)
閰嶇敤锛� EVAL-AD2S1210EDZ-ND - BOARD EVAL AD2S1210
AD2S1210
Rev. A | Page 6 of 36
TIMING SPECIFICATIONS
AVDD = DVDD = 5.0 V 卤 5%, TA = TMIN to TMAX, unless otherwise noted.1
Table 2.
Parameter
Description
Limit at TMIN, TMAX
Unit
fCLKIN
Frequency of clock input
6.144
MHz min
10.24
MHz max
tCK
Clock period ( = 1/fCLKIN)
98
ns min
163
ns max
t1
A0 and A1 setup time before RD/CS low
2
ns min
t2
Delay CS falling edge to WR/FSYNC rising edge
22
ns min
t3
Address/data setup time during a write cycle
3
ns min
t4
Address/data hold time during a write cycle
2
ns min
t5
Delay WR/FSYNC rising edge to CS rising edge
2
ns min
t6
Delay CS rising edge to CS falling edge
10
ns min
t7
Delay between writing address and writing data
2 脳 tCK + 20
ns min
t8
A0 and A1 hold time after WR/FSYNC rising edge
2
ns min
t9
Delay between successive write cycles
6 脳 tCK + 20
ns min
t10
Delay between rising edge of WR/FSYNC and falling edge of RD
2
ns min
t11
Delay CS falling edge to RD falling edge
2
ns min
t12
Enable delay RD low to data valid in configuration mode
VDRIVE = 4.5 V to 5.25 V
37
ns min
VDRIVE = 2.7 V to 3.6 V
25
ns min
VDRIVE = 2.3 V to 2.7 V
30
ns min
t13
RD rising edge to CS rising edge
2
ns min
t14A
Disable delay RD high to data high-Z
16
ns min
t14B
Disable delay CS high to data high-Z
16
ns min
t15
Delay between rising edge of RD and falling edge of WR/FSYNC
2
ns min
t16
SAMPLE pulse width
2 脳 tCK + 20
ns min
t17
Delay from SAMPLE before RD/CS low
6 脳 tCK + 20
ns min
t18
Hold time RD before RD low
2
ns min
t19
Enable delay RD/CS low to data valid
VDRIVE = 4.5 V to 5.25 V
17
ns min
VDRIVE = 2.7 V to 3.6 V
21
ns min
VDRIVE = 2.3 V to 2.7 V
33
ns min
t20
RD pulse width
6
ns min
t21
A0 and A1 set time to data valid when RD/CS low
VDRIVE = 4.5 V to 5.25 V
36
ns min
VDRIVE = 2.7 V to 3.6 V
37
ns min
VDRIVE = 2.3 V to 2.7 V
29
ns min
t22
Delay WR/FSYNC falling edge to SCLK rising edge
3
ns min
t23
Delay WR/FSYNC falling edge to SDO release from high-Z
VDRIVE = 4.5 V to 5.25 V
16
ns min
VDRIVE = 2.7 V to 3.6 V
26
ns min
VDRIVE = 2.3 V to 2.7 V
29
ns min
t24
Delay SCLK rising edge to DBx valid
VDRIVE = 4.5 V to 5.25 V
24
ns min
VDRIVE = 2.7 V to 3.6 V
18
ns min
VDRIVE = 2.3 V to 2.7 V
32
ns min
t25
SCLK high time
0.4 脳 tSCLK
ns min
t26
SCLK low time
0.4 脳 tSCLK
ns min
t27
SDI setup time prior to SCLK falling edge
3
ns min
t28
SDI hold time after SCLK falling edge
2
ns min
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
AD2S1210BSTZ-DASSAULT 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:
AD2S1210CSTZ 鍔熻兘鎻忚堪:IC CONV R/D VAR RES OSC 48-LQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - ADCs/DAC - 灏堢敤鍨� 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:50 绯诲垪:- 椤炲瀷:鏁�(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)锛圖AS锛� 鍒嗚鲸鐜囷紙浣嶏級:16 b 閲囨ǎ鐜囷紙姣忕锛�:21.94k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:MICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI? 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 闆绘簮闆诲:1.8 V ~ 3.6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:40-WFQFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:40-TQFN-EP锛�6x6锛� 鍖呰:鎵樼洡
AD2S1210DSTZ 鍔熻兘鎻忚堪:IC CONV R/D VAR RES OSC 48LQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - ADCs/DAC - 灏堢敤鍨� 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:50 绯诲垪:- 椤炲瀷:鏁�(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)锛圖AS锛� 鍒嗚鲸鐜囷紙浣嶏級:16 b 閲囨ǎ鐜囷紙姣忕锛�:21.94k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:MICROWIRE?锛孮SPI?锛屼覆琛岋紝SPI? 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 闆绘簮闆诲:1.8 V ~ 3.6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:40-WFQFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:40-TQFN-EP锛�6x6锛� 鍖呰:鎵樼洡
AD2S1210DSTZ 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:IC, ADC, 16BIT, PARALLEL, SERIAL, LQFP-4
AD2S1210SST-EP-RL7 鍔熻兘鎻忚堪:妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 - ADC IC 10-16 Bit R/D Cnvtr w/Ref Oscilltr RoHS:鍚� 鍒堕€犲晢:Analog Devices 閫氶亾鏁�(sh霉)閲�: 绲�(ji茅)妲�(g貌u): 杞�(zhu菐n)鎻涢€熺巼: 鍒嗚鲸鐜�: 杓稿叆椤炲瀷: 淇″櫔姣�: 鎺ュ彛椤炲瀷: 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�: 灏佽 / 绠遍珨: