參數(shù)資料
型號(hào)： AD2S1205YSTZ
廠(chǎng)商： ANALOG DEVICES INC
元件分類(lèi)： 位置變換器
英文描述： 12-Bit R/D Converter with Reference Oscillator
中文描述： SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, PQFP44
封裝： LEAD FREE, MS-026BCB, LQFP-44
文件頁(yè)數(shù)： 21/25頁(yè)
文件大小： 367K
代理商： AD2S1205YSTZ
Preliminary Technical Data
AD2S1205
CLOCK REQUIREMENTS
To achieve the specified dynamic performance, an external
crystal is recommended at the CLKIN, XTALOUT pins. The
position and velocity accuracy are guaranteed for operation
with a range of input frequencies from 6.144MHz to 10.24
MHz., based around a nominal value of 8.192 MHz. The
velocity outputs are scaled in proportion to the clock frequency
so that if the clock is 25% higher than the nominal, the full-
scale velocity will be 25% higher than nominal. The maximum
tracking rate, the tracking loop bandwidth and the excitation
output frequencies also vary with the clock frequency.
Rev. PrB | Page 21 of 25
CONNECTING TO THE DSP
The AD2S1205 serial port is ideally suited for interfacing to
DSP configured microprocessors. Figure 16 shows the
AD2S1205 interfaced to ADMC401, one of the DSP based
motor controllers.
The on-chip serial port of the ADMC401 is used in the
following configuration:
Alternate framing transmit mode with internal framing
(internally inverted)
Normal framing receive mode with external framing
(internally inverted)
Internal serial clock generation
In this mode, the ADMC401 uses the internal TFS signal as
external RFS to fully control the timing of receiving data and it
uses the same TFS as RD to the AD2S1205. The ADMC401 also
provides an internal continuous serial clock to the AD2S1205.
The SAMPLE signal on the AD2S1205 could be provided either
by using a PIO or by inverting the PWMSYNC signal to
synchronize the position and velocity reading with the PWM
switching frequency. CS and RDVEL may be obtained using
two PIO outputs of the ADMC401. The 12 bits of significant
data plus status bits are available on each consecutive negative
edge of the clock following the low going of the RD signal. Data
is clocked from the AD2S1205 into the data receive register of
the ADMC401. This is internally set to 16 bits (12 bits data, 4
status bits) because 16 bits are received overall. The serial port
automatically generates an internal processor interrupt. This
allows the ADMC401 to read 16 bits at once and continue
processing.
All ADMC401 products can interface to the AD2S1205 with
similar interface circuitry.
0
SCLK
DR
TFS
RFS
PWMSYNC
PIO
PIO
SCLK
SOE
SO
RD
SAMPLE
CS
RDVEL
ADMC401
AD2S1205
Figure 16. Connecting to the ADMC401
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