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參數(shù)資料
| 型號： | AD2S1205 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit R/D Converter with Reference Oscillator |
| 中文描述： | 12位的R / D轉(zhuǎn)換器與參考振蕩器 |
| 文件頁數(shù)： | 17/25頁 |
| 文件大?。?/td> | 367K |
| 代理商： | AD2S1205 |
Preliminary Technical Data
AD2S1205
At 12 bits, the PPR = 1,024. Therefore, the maximum speed,
n
,
of the AD2S1205 is
Rev. PrB | Page 17 of 25
rpm
n
60000
024
,
000
,
024
,
×
60
=
=
To get a maximum speed of 60,000 rpm, an external crystal of
8.192 MHz has to be chosen in order to produce an internal
CLOCKOUT equal to 4.096 MHz.
This compares favorably with encoder specifications where f
MAX
is specified from 20 kHz (photo diodes) to 125 kHz (laser
based) depending on the light system used. A 1,024 line laser-
based encoder will have a maximum speed of 7,300 rpm.
The inclusion of A, B outputs allows the AD2S1205 plus
resolver solution to replace optical encoders directly without
the need to change or upgrade existing application software.
ON-BOARD PROGRAMMABLE SINUSOIDAL
OSCILLATOR
An on-board oscillator provides the sinusoidal excitation signal
(EXC) to the resolver as well as its complemented signal (EXC).
The frequency of this reference signal is programmable to four
standard frequencies (10 kHz, 12 kHz, 15 kHz, or 20 kHz) using
the FS1 and FS2 pins (see Table 7). FS1 and FS2 have internal pull-
ups, so the default frequency is 10 kHz. The amplitude of this
signal is centered on 2.5 V and has an amplitude of 3.6 V p-p.
Table 7. Excitation Frequency Selection
Frequency Selection (kHz)
10
12
15
20
The reference output of the AD2S1205 will need an external
buffer amplifier to provide gain and the additional current to
drive a resolver. Refer to Figure 6 for a suggested buffer circuit.
FS1
1
1
0
0
FS2
1
0
1
0
The AD2S1205 also provides an internal synchronous reference
signal that is phase locked to its Sin and Cos inputs. Phase
errors between the resolver primary and secondary windings
could degrade the accuracy of the RDC and are compensated by
this synchronous reference signal. This also compensates the
phase shifts due to temperature and cabling and eliminates the
need of an external preset phase compensation circuits.
Synthetic Reference Generation
When a resolver undergoes a high rotation rate, the RDC tends
to act as an electric motor and produces speed voltages, along
with the ideal Sin and Cos outputs. These speed voltages are in
quadrature to the main signal waveform. Moreover, nonzero
resistance in the resolver windings causes a non-zero phase shift
between the reference input and the Sin and Cos outputs. The
combination of speed voltages and phase shift causes a tracking
error in the RDC that is approximated by
Frequency
Reference
Rate
Rotation
Shift
Phase
Error
×
=
To compensate for the described phase error between the
resolver reference excitation and the Sin/Cos signals, an internal
synthetic reference signal is generated in phase with the refer-
ence frequency carrier. The synthetic reference is derived using
the internally filtered Sin and Cos signals. It is generated by
determining the zero crossing of either the Sin or Cos (which-
ever signal is larger, to improve phase accuracy) and evaluating
the phase of the resolver reference excitation. The synthetic
reference reduces the phase shift between the reference and
Sin/Cos inputs to less than 10°, and will operate for phase shifts
of ±45°.
SUPPLY SEQUENCING AND RESET
The AD2S1205 requires an external reset signal to hold the
RESET input low until V
DD
is within the specified operating
range of 4.5 V to 5.5 V.
The RESET pin must be held low for a minimum of 10 μs after
V
DD
is within the specified range (t
RST
in Figure 10). Applying a
RESET signal to the AD2S1205 initializes the output position to
a value of 0x000 (degrees output through the parallel, serial, and
encoder interfaces) and causes LOS to be indicated (LOT and
DOS pins pulled low) as shown in Figure 10.
Failure to apply the above (correct) power-up/reset sequence
can result in an incorrect position indication.
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