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參數(shù)資料
| 型號： | AD2S100AP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理外設 |
| 英文描述： | AC Vector Processor |
| 中文描述： | 12-BIT, DSP-COORDINATE TRANSFORM PROCESSOR, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 393K |
| 代理商： | AD2S100AP |
AD2S100
TIMING DIAGRAMS
Busy Output
The state of converter is indicated by the state of the BUSY out-
put (Pin 44). The BUSY output will go HI at the negative edge
of the STROBE input. This is used to synchronize digital input
data and load the digital angular rotation information into the
device counter. The BUSY output will remain HI for 2
μ
s, and
go LO until the next strobe negative edge occurs.
REV. A
–8–
Strobe Input
The width of the positive STROBE pulse should be at least
100 ns, in order to successfully start the conversion. The maxi-
mum frequency of STROBE input is 366 kHz, i.e., there should
be at least 2.73
μ
s from the negative edge of one STROBE pulse
to the next rising edge. This is illustrated by the following tim-
ing diagram and table.
t
1
t
2
t
3
t
4
STROBE
BUSY
t
f
t
r
Figure 7. AD2S100 Timing Diagram
Note: Digital data should be stable 25 ns before and after posi-
tive strobe edge.
Table II. AD2S100 Timing Table
Parameter
Min
Typ
Max
Condition
t
1
t
2
t
3
t
4
t
r
100 ns
STROBE Pulse Width
STROBE
↓
to BUSY
↑
BUSY Pulse Width
BUSY
↓
to STROBE
↑
BUSY Pulse Rise Time
with No Load
BUSY Pulse Rise Time
with 68 pF Load
BUSY Pulse Fall Time
with No Load
BUSY Pulse Fall Time
with 68 pF Load
30 ns
1.7
μ
s
2.5
μ
s
100 ns
20 ns
150 ns
t
f
10 ns
120 ns
TYPICAL CIRCUIT CONFIGURATION
Figure 8 shows a typical circuit configuration for the AD2S100
in a three phase, nominal level input mode (MODE2).
T
AD2S100
TOP VIEW
1
41
38
30
27
23
12
PH/IP3
16
PH/IP1
D
LSB
S
C
10μF
100nF
10μF
100nF
–5V
+5V
GND
T
O
S
B
H
H
H
MSB
PH/OP1
PH/OP3
PH/OP2
AGND
PH/IP4
PH/IP2
34
Figure 8. Typical Circuit Configuration
APPLICATIONS
Forward and ReverseTransformation
The AD2S100 can perform both forward and reverse transfor-
mations. The section “Theory of Operation” explains how the
chip operates with the core operator e
+j
φ
, which performs a for-
ward transformation. The reverse transformation, e
–j
φ
, is not
mentioned in the above sections of the data sheet simply to
avoid the confusion in the functionality and pinout. However,
the reverse transformation is very useful in many different appli-
cations, and the AD2S100 can be easily configured in a reverse
transformation configuration. Figure 9 shows four different
phase input/output connections for AD2S100 reverse transfor-
mation operation.
–1
3 PHASE – 3 PHASE
e
–j
φ
–1
e
+j
φ
e
+j
φ
e
+j
φ
e
+j
φ
2 PHASE – 2 PHASE
2 PHASE – 3 PHASE
3 PHASE – 2 PHASE
FORWARD
TRANSFORMATION
AD2S100
Cos
θ
Cos(
θ
+ 120
°
)
Cos(
θ
+ 240
°
)
REVERSE
TRANSFORMATION
AD2S100
Sin
θ
Cos(
θ
+
φ
)
Cos(
θ
+
φ
+ 120
°
)
Cos(
θ
+
φ
+ 240
°
)
Cos
θ
Sin
θ
Cos
θ
Cos
θ
Cos(
θ
+ 120
°
)
Cos(
θ
+ 240
°
)
Cos(
θ
+
φ
)
Sin(
θ
+
φ
)
Cos(
θ
+
φ
)
Cos(
θ
+
φ
+ 120
°
)
Cos(
θ
+
φ
+ 240
°
)
Cos(
θ
+
φ
)
Sin(
θ
+
φ
)
Cos
θ
Cos(
θ
+ 120
°
)
Cos(
θ
+ 240
°
)
Cos(
θ
–
φ
)
Cos(
θ
–
φ
+ 120
°
)
Cos(
θ
–
φ
+ 240
°
)
Cos(
θ
–
φ
)
Cos(
θ
–
φ
+ 120
°
)
Cos(
θ
–
φ
+ 240
°
)
Cos
θ
Sin
θ
Cos(
θ
–
φ
)
Sin(
θ
–
φ
)
Cos
θ
Sin
θ
Cos
θ
Cos(
θ
+ 120
°
)
Cos(
θ
+ 240
°
)
Cos(
θ
–
φ
)
Sin(
θ
–
φ
)
e
–j
φ
e
–j
φ
e
–j
φ
Figure 9. Reverse Transformation Connections
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