參數(shù)資料
型號(hào): AD260
廠商: Analog Devices, Inc.
英文描述: High Speed, Logic Isolator with Power Transformer(數(shù)字隔離放大器)
中文描述: 高速,邏輯與電力變壓器(數(shù)字隔離放大器隔離)
文件頁(yè)數(shù): 2/8頁(yè)
文件大?。?/td> 180K
代理商: AD260
–2–
REV. 0
AD260–SPECIFICATIONS
(Typical at T
A
= +25
8
C, +5 V dc
SYS
, +5 V dc
FLD
, t
RR
= 50 ns max unless otherwise noted)
Parameter
Conditions
Min
Typ
Max
Units
INPUT CHARACTERISTICS
Threshold Voltage
Positive Transition (V
T+
)
+5 V dc
SYS
= 4.5 V
+5 V dc
SYS
= 5.5 V
+5 V dc
SYS
= 4.5 V
+5 V dc
SYS
= 5.5 V
+5 V dc
SYS
= 4.5 V
+5 V dc
SYS
= 5.5 V
2.0
3.0
0.9
1.2
0.4
0.5
2.7
3.2
1.8
2.2
0.9
1.0
5
0.5
3.15
4.2
2.2
3.0
1.4
1.5
V
V
V
V
V
V
pF
μ
A
Negative Transition (V
T–
)
Hysteresis Voltage (V
H
)
Input Capacitance (C
IN
)
Input Bias Current (I
IN
)
Per Input
OUTPUT CHARACTERISTICS
Output Voltage
High Level (V
OH
)
+5 V dc
SYS
= 4.5 V, |I
O
| = 0.02 mA
+5 V dc
SYS
= 4.5 V, |I
O
| = 4 mA
+5 V dc
SYS
= 4.5 V, |I
O
| = 0.02 mA
+5 V dc
SYS
= 4.5 V, |I
O
| = 4 mA
ENABLE
SYS/FLD
@ Logic Low/High Level Respectively
4.4
3.7
V
V
V
V
μ
A
Low Level (V
OL
)
0.1
0.4
Output Three-State Leakage Current
0.5
DYNAMIC RESPONSE
1
(Refer to Figure 2)
Max Logic Signal Frequency (f
MIN
)
Waveform Edge Symmetry Error (t
ERROR
)
Logic Edge Propagation Delay (t
PHL
PLH
)
Minimum Pulsewidth (t
PWMIN
)
Max Output Update Delay on Fault or After
Power-Up Reset Interval (
30
μ
s
)
2
50% Duty Cycle, +5 V dc
SYS
= 5 V
t
PHL
vs. t
PLH
20
MHz
ns
ns
ns
±
1
14
25
25
12
μ
s
ISOLATION BARRIER RATING
3
Operating Isolation Voltage (V
CMV
)
AD260A
AD260B
AD260A
AD260B
375
1250
V rms
V rms
V rms
V rms
V/
μ
s
pF
μ
A rms
Isolation Rating Test Voltage (V
CMV TEST
)
4
1750
3500
10,000
Transient Immunity (V
TRANSIENT
)
Isolation Mode Capacitance (C
ISO
)
Capacitive Leakage Current (I
LEAD
)
Total Capacitance, All Lines and Transformer
240 V rms @ 60 Hz
14
18
2
POWER TRANSFORMER
Primary Winding
Inductance (LP)
Number of Turns (NP)
Resistance
Max Volt-Seconds (E
×
t)
Recommended Operating Frequency
Absolute Min Operating Frequency
Secondary Winding
Number of Turns (NS)
Resistance
Insulation Withstand (V
CMV TEST
)
Capacitance
Recommended Max Power
Bifilar Wound, Center-Tapped
Each Half
Each Half
Each Half
Each Half
–25
°
C to +85
°
C, Push-Pull Drive
–25
°
C to +85
°
C, Push-Pull Drive
Bifilar Wound, Center-Tapped
Each Half
Each Half
Primary to Secondary
Primary to Secondary
Rated Performance
1
26
0.6
mH
Turns
V
×
μ
s
kHz
kHz
27
300
150
75
200
48
2.3
Turns
V rms
pF
W
3,500
5
1.0
1.5
POWER SUPPLY
Supply Voltage (+5 V dc
SYS
and +5 V dc
FLD
)
Rated Performance
Operating
Effective, per Input, Either Side
Effective per Output, Either Side—No Load
Each, +5 V dc
SYS & FLD
All Lines @ 10 MHz (Sum of +5 V dc
SYS & FLD
)
4.5
4.0
5.5
5.75
V dc
V dc
pF
pF
mA
mA
Power Dissipation Capacitance
8
28
4
18
Quiescent Supply Current
Supply Current
TEMPERATURE RANGE
Rated Performance (T
A
)
5
Storage (T
STG
)
–25
–40
+85
+85
°
C
°
C
NOTES
1
For best performance, bypass +5 V dc supplies to com. at or near the device (0.01
μ
F). +5 V dc supplies are also internally bypassed with 0.05
μ
F.
2
As the supply voltage is applied to either side of the AD260, the internal circuitry will go into a power-up reset mode (all lines disabled) for about 30
μ
s after the point where
+5 V dc
SYS & FLD
passes above 3.3 V.
3
“Operating” isolation voltage is derived from the Isolation Test Voltage in accordance with such methods as found in VDE-0883 wherein a device will be “hi-pot” tested at twice
the operating voltage, plus one thousand volts. Partial discharge testing, with an acceptance threshold of 80 pC of discharge may be considered the same as a hi-pot test (but
nondestructive).
4
Partial Discharge at 80 pC THLD.
5
Supply Current will increase slightly, but otherwise the unit will function within specification to –40
°
C.
Specifications are subject to change without notice.
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