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參數(shù)資料
| 型號： | AD1994ACPZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | Audio Switching Amplifier |
| 中文描述： | 25 W, 2 CHANNEL, AUDIO AMPLIFIER, QCC64 |
| 封裝： | 9 X 9 MM, LEAD FREE, MO-220VMMD-4, LFCSP-64 |
| 文件頁數(shù)： | 17/24頁 |
| 文件大?。?/td> | 377K |
| 代理商： | AD1994ACPZRL |
AD1994
Setting the Modulator Gain
The AD1994 modulator uses a combination of the input signal
and feedback from the power output stage to calculate its two-
state output pattern. The feedback input nodes are part of the
internal analog circuit that operates from the AV
5 V) power supply. Because the voltage measured at the power
outputs is nominally between 0 V and PV
DD
, and thus beyond
the 0 V to AV
feedback to an appropriate level.
Rev. 0 | Page 17 of 24
Programmable Gain Amplifier (PGA)
The Σ-Δ modulator itself requires a fixed gain for a given value
of PV
but many applications require more gain to account for low
source signal levels. The AD1994 includes a programmable gain
amplifier (PGA) to boost the overall amplifier gain. PGA1 (Pin
31) and PGA0 (Pin 32) select one of four PGA gain values, as
shown in
Table 11.
DD
to maintain optimal stability. This gain can be appropriate,
DD
(nominal
DD
range, a voltage divider is required to scale the
Table 11. PGA Gain Settings
PGA1
0
0
1
1
Resistor voltage dividers should sense the voltage on each side
of the differential output and provide these feedback signals to
the modulator, as shown in
Figure 45.
PGA0
0
1
0
1
PGA Gain (dB)
0
6
12
18
EXTERNAL COMPONENTS
R1
R3
C
C
L
L
R
L
D2
D4
D1
D3
OUTx+
OUTx–
R2
R4
PV
DD
PV
DD
NFx+
NFx–
PGND
PGND
0
Figure 45. H-Bridge Configuration
The resistor values should satisfy the following equation to
maintain modulator stability.
4
3
2
R
R
635
.
4
2
1
DD
PV
R
R
R
R
Gain
=
+
=
+
=
Selecting a gain that meets this criterion ensures that the
modulator remains in a stable operating condition.
The ratio of the resistances sets the gain rather than the absolute
values. However, the dividers provide a path from the high
voltage supply to ground; therefore, the values should be large
enough to produce negligible loss due to quiescent current.
The chip contains a calibration circuit to minimize voltage
offsets at the speaker, which helps to minimize clicks and pops
when muting or unmuting. Optimal performance is achieved
for the offset calibration circuit when the feedback divider resistors
sum to 6 kΩ, that is, (R1 + R2) = 6 kΩ, and (R3 + R4) = 6 kΩ.
Table 10. Recommended Feedback Resistor Values
PV
DD
(V)
R1 (kΩ)
12
4.2
15
4.55
18
4.8
20
4.91
R2 (kΩ)
1.8
1.45
1.2
1.09
Gain
3.3 (+10.4 dB)
4.1 (+12.3 dB)
5.0 (+14.0 dB)
5.5 (+14.8 dB)
The AD1994 incorporates a single-ended-to-differential
converter for each channel in the analog front-end section.
The PGA is also part of this analog front-end, and it affects the
analog input signal before it enters the Σ-Δ modulator. The
PGA1 and PGA0 pins are continuously monitored and allow
the gain to be changed at any time.
POWER STAGE
The H-Bridge
The output stage of the AD1994 includes four integrated
MOSFET devices arranged in a full H-bridge, as shown in
Figure 45. The P-Type, high-side transistor of one leg and the
N-Type, low-side transistor of the opposite leg switch on and off
as a pair producing a total voltage swing across the load of
PV
DD
to +PV
DD
. The drive is floating and differential, and it is
important that neither output terminal be shorted to ground.
The power supply for the output stage of the AD1994, PV
DD
,
should be in the 8 V to 20 V range and should be capable of
supplying enough current to drive the load. Connect the power
supply across the PVDD and PGND pins. The feedback pins,
NFR+, NFR, NFL+, and NFL, supply negative feedback to
the modulator as described in the Setting the Modulator Gain
section.
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