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參數(shù)資料
| 型號： | AD1984JCPZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | High Definition Audio SoundMAX Codec |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC48 |
| 封裝： | 7 X 7 MM, LEAD FREE, MO-220VKKD-2, LFCSP-48 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 283K |
| 代理商： | AD1984JCPZ |
Rev. 0
|
Page 12 of 20
|
January 2007
AD1984
DIGITAL MICROPHONE INTERFACE TIMING SPECIFICATIONS
The digital microphone interface can support one, two, or four
digital microphones using two or three codec pins. Both uniplex
(one mic per data pin) and multiplex (two mics sharing the
same data pin) are supported. These configurations are shown
in
Figure 3
,
Figure 4
,
Figure 6
, and
Figure 7
. The interface can
generate a microphone clock at 1.5 MHz, 2.0 MHz, or 3.0 MHz
to suit quality and power requirements.
Table 4. Digital Microphone Timing Parameters
Parameter
Timing Requirements
t
0
Min
Typ
Max
Unit
DM_CLK (1.5 MHz) Period
Duty Cycle
DM_CLK (2.0 MHz) Period
Duty Cycle
DM_CLK (3.0 MHz) Period
Duty Cycle
DM_CLK Rise Time
DM_CLK Fall Time
DM_CLK Edge to Data Valid
Data Setup to DM_CLK Edge
Data Hold from DM_CLK Edge
DM_CLK Edge to Data Hi-Z
667
60/40
500
50/50
333
50/50
ns
%
ns
%
ns
%
ns
ns
ns
ns
ns
ns
t
0
t
0
t
1
t
2
t
3
t
4
t
5
t
6
5
5
40
100
5
7
Figure 3. Uniplex Digital Microphone, Mono Interface
GAM
MUX
D
Q
D
Q
>
GAM
GAM
GAM
NID:06
DIGITAL FILTER
NID:05
DIGITAL FILTER
H
DM-CLK
GENERATOR
S
WAPL/R
ON CHIP
OFF-CHIP
LEFT
RIGHT
LEFT
RIGHT
DM_1/2
DM_
3
/4
DM_CLK
MIC 1
>
D
Q
D
Q
>
>
GAM = GAIN, ATTENUATE, MUTE
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