參數(shù)資料
型號(hào)： AD1981BLJSTZ2
廠商： Analog Devices, Inc.
元件分類： Codec
英文描述： AC ’97 SoundMAX㈢ Codec
中文描述： ㈢交流\u0026#39;97 SoundMAX編解碼器
文件頁數(shù)： 23/28頁
文件大?。?/td> 215K
代理商： AD1981BLJSTZ2
REV. 0
AD1981BL
–23–
CFD[15:0]
Coefficient Data. The biquad coefficients are fixed point format values with 16 bits of resolution. The CFD15 bit is
the MSB, and the CFD0 bit is the LSB.
RMG[3:0]
Right Mixer Gain Control. This register controls the gain into the mixer ADC from 0 dB to a maximum gain of
22.5 dB. The least significant bit represents 1.5 dB.
RM
Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately
from the MXM bit. Otherwise, this bit will always read 0 and will have no affect when set to 1.
LMG[3:0]
Left Mixer Gain Control. This register controls the gain into the mixer ADC, from 0 dB to a maximum gain of 22.5 dB.
The least significant bit represents 1.5 dB.
MXM
Mixer Gain Register Mute.
0 = Unmuted.
1 = Muted (reset default).
EQ Data Register (Index 62h)
Reg
No. Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
62h EQ DATA CFD15 CFD14 CFD13 CFD12 CFD11 CFD10 CFD9 CFD8 CFD7 CFD6 CFD5 CFD4 CFD3 CFD2 CFD1 CFD0 0000h
This read/write register is used to transfer EQ biquad coefficients into memory. The register data is transferred to, or retrieved from, the address pointed to by the
BCA bits in the EQ CNTRL Register (60h). Data will be written to memory only if the EQM bit (Register 60h, Bit 15) is asserted.
Mixer ADC, Input Gain Register (Index 64h)
Reg
No. Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
64h Mixer
Volume
MXM X
X
X
LMG3 LMG2
LMG1
LMG0
RM
*
X
X
X
RMG3 RMG2 RMG1
RMG0 8000h
*
For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right
channels. If MSPLT is not set, the RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table VII for examples.
Table VII. Settings for Mixer ADC, Input Gain
Control Bits
Reg. 76h
Mixer ADC, Input Gain (64h)
Left Channel Mixer Gain D[11:8]
Right Channel Mixer Gain D[3:0]
MSPLT
*
D15 Write
Readback
Function
D7
*
Write
Readback
Function
0
0
1111
1111
22.5 dB Gain
x
1111
1111
22.5 dB Gain
0
0
0000
0000
0 dB Gain
x
0000
0000
0 dB Gain
0
1
xxxx
xxxx
– dB Gain, Muted
x
xxxx
xxxx
– dB Gain, Muted
1
0
1111
1111
22.5 dB Gain
1
xxxx
xxxx
– dB Gain,
Right Only Muted
1
1
xxxx
xxxx
– dB Gain, Left Only Muted 0
1111
1111
22.5 dB Gain
1
1
xxxx
xxxx
– dB Gain, Left Muted
1
xxxx
xxxx
– dB Gain,
Right Muted
*
For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right
channels. If MSPLT is not set, RM bit has no effect.
x is a wild card and has no effect on the value.
相關(guān)PDF資料
PDF描述
AD1981BLJSTZ-REEL2 AC ’97 SoundMAX㈢ Codec
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD1981BLJSTZ-REEL 制造商:Analog Devices 功能描述:Audio Codec 4ADC / 2DAC 20-Bit 48-Pin LQFP T/R
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AD1981BWBSTZ 制造商:Analog Devices 功能描述:
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AD1981HD 制造商:AD 制造商全稱:Analog Devices 功能描述:HD Audio SoundMAX Codec
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