參數(shù)資料
型號: AD1970
廠商: Analog Devices, Inc.
英文描述: Digital BTSC Encoder with Integrated ADC and DAC
中文描述: 數(shù)字廣播電視系統(tǒng)委員會編碼器與集成ADC和DAC
文件頁數(shù): 12/20頁
文件大?。?/td> 278K
代理商: AD1970
AD1970
CONTROL PORT
I
2
C PORT OVERVIEW
The AD1970 can be controlled using the I
2
C port. In general,
there are three parameters that can be controlled: the encoder
output level, the Phat Stereo image enhancement algorithm, and
the dialog enhancement algorithm. It is also possible to write
new data into the parameter RAM to alter the filter coefficients
used in the BTSC encoding process. Since this is a fairly
complex topic and is unnecessary for normal operation of the
chip, the details are not included in this data sheet; please
contact ADI sales if modifications to the BTSC filters are
required.
Rev. 0 | Page 12 of 20
The I
2
C port uses a 2-wire interface consisting of SDA, the
bidirectional data line, and SCL, the clock.
The R/W bit is low for a write operation and high for a read
operation. The 10-bit address word is decoded into either a
location in the parameter RAM or one of the registers. The
number of data bytes varies according to the register or
memory being accessed. The detailed data format diagram for
continuous-mode operation is given in the section.
I
2
C ADDRESS DECODING
Table 16 shows the address decoding used in the I
2
C port. Four
different addresses are available to avoid conflicting addresses
on an I
2
C bus. The I
2
C address space encompasses a set a
registers and the parameter RAM. The parameter RAM is
loaded on power-up from an on-board boot ROM.
Table 16. I
2
C Address Settings
ADR1
ADR0
0
0
0
1
1
0
1
1
I
2
C Address
0x20
0x21
0x22
0x23
Table 17. I
2
C Port Address Decoding
Register Address
0
Register Name
Input Level Control
Read/Write Word Length
Write: 22 bits
Read: 22 bits
Write: 11 bits
Read: 6 bits
Write: 22 bits
1 to 254
255
256
Parameter RAM
Output Level Control
Control Register 1
257
258
259
260
Control Register 2
ADC Volume Control
Stereo Spreading Control
Dialog Enhancement Control
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