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參數(shù)資料
| 型號(hào)： | AD1959YRS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | PLL/Multibit DAC |
| 中文描述： | SERIAL INPUT LOADING, DAC WITH PROGRAMMABLE PLL, PDSO28 |
| 封裝： | PLASTIC, SSOP-28 |
| 文件頁(yè)數(shù)： | 7/8頁(yè) |
| 文件大?。?/td> | 107K |
| 代理商： | AD1959YRS |
REV. 0
AD1959
–7–
POWER SUPPLY AND VOLTAGE REFERENCE
The AD1959 is designed for five-volt supplies. Separate power
supply pins are provided for the analog, digital, and PLL sec-
tions. These pins should be bypassed with 100 nF ceramic chip
capacitors, as close to the pins as possible, to minimize noise. A
bulk aluminum electrolytic capacitor of at least 22
μ
F should
also be provided on the same PC board. For best performance it
is recommended that the analog supply be separate from the
digital and PLL supply. It is recommended that all supplies be
isolated by ferrite beads in series with each supply. It is expected
that the digital and PLL sections will be run from a common
supply but isolated from one another. It is important that the
analog supply be as clean as possible.
The internal voltage reference is brought out on Pin 21 (FILTR)
and should be bypassed as close as possible to the chip with a
parallel combination of 10
μ
F and 100 nF The reference voltage
may be used to bias external op amps to the common-mode
voltage of the analog output signal pins. The current drawn
from the V
REF
pin should be limited to less than 50
μ
A.
SERIAL DATA PORTS – DATA FORMAT
The DAC serial data input mode defaults to I
2
S. By changing
Bits 4 and 5 in the DAC control register, the mode can be
changed to RJ, DSP, or LJ. The word width defaults to 24 bits
but can be changed by programming Bits 8 and 9 in the DAC
Control Register.
Figure 2 shows the serial mode formats.
LRCLK
BCLK
SDATA
LRCLK
BCLK
SDATA
LRCLK
BCLK
SDATA
LRCLK
BCLK
SDATA
LEFT CHANNEL
RIGHT CHANNEL
LEFT CHANNEL
RIGHT CHANNEL
LEFT CHANNEL
RIGHT CHANNEL
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LEFT-JUSTIFIED MODE – 16 TO 24 BITS PER CHANNEL
1
2
S MODE – 16 TO 24 BITS PER CHANNEL
RIGHT-JUSTIFIED MODE – SELECT NUMBER OF BITS PER CHANNEL
DSP MODE – 16 TO 24 BITS PER CHANNEL
1/f
S
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL.
2. LRCLK NORMALLY OPERATES AT f
S
EXCEPT FOR DSP MODE WHICH IS 2
f
.
3. BCLK FREQUENCY IS NORMALLY 64
LRCLK BUT MAY BE OPERATED IN BURST MODE.
Figure 2. Stereo Serial Modes
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AD1959YRSRL | 制造商:Analog Devices 功能描述:DAC 2-CH Delta-Sigma 24-bit 28-Pin SSOP T/R 制造商:Rochester Electronics LLC 功能描述:HIGH PERFORMANCE DAC,105DB DYNAMIC RANGE - Tape and Reel |
| AD1959YRSZRL | 制造商:Analog Devices 功能描述:DAC 2-CH Delta-Sigma 24-bit 28-Pin SSOP T/R |
| AD-1962-CV1648-PR.RFL- | 制造商:TE Connectivity 功能描述:AD-1962-CV1648-PR.RFL-ADP 989172-000 |
| AD-1962-CV1648-PR.RFL-ADP | 制造商:TE Connectivity 功能描述: 制造商:TE Connectivity 功能描述:AD-1962-CV1648-PR.RFL-ADP |
| AD1970 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Digital BTSC Encoder with Integrated ADC and DAC |
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