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參數(shù)資料
| 型號： | AD1958YRS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | PLL/Multibit DAC |
| 中文描述： | SERIAL INPUT LOADING, DAC WITH PROGRAMMABLE PLL, PDSO28 |
| 封裝： | PLASTIC, SSOP-28 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 135K |
| 代理商： | AD1958YRS |
REV. 0
AD1958
–6–
Table I. DAC Control Register
Bit 11:10
Bit 9:8
Bit 7
Bit 6
Bit 5:4
Bit 3:2
Bit 1:0
Interpolation
Factor
Serial Data
Width
Serial Data
Format
De-Emphasis
Filter
SPI Register
Address
Output Phase
Soft Mute
00 = 8
×
*
01 = 4
×
10 = 2
×
11 = Not Allowed
00 = 24 Bits
*
01 = 20 Bits
10 = 16 Bits
11 = 16 Bits
0 = Noninverted
*
1 = Inverted
0 = No Mute
*
1 = Muted
00 = I
2
S
*
00 = Right Justified
10 = DSP
11 = Left Justified
00 = None
*
01 = 44.1 kHz
10 = 32 kHz
11 = 48 kH
z
01
*
Default Setting
Table III. PLL Control Register
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7:6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1:0
PLL2
Power-
Down
0 = On
1
1 = PD
PLL1
Power-
Down
0 = On
1
1 = PD
XTAL
Power-
Down
0 = On
1
1 = PD
SPI
Register
Address
Clock
Configuration
0 = Mode 0
1
SCLK1
Select
Frequency
Double
2
SCLK2
Select
MCLK
Mode
0 = Output
1
1 = Input
f
S
SCLK1 =
000: 36.864 MHz
1
100: 24.576 MHz
110: 33.8688 MHz
111: 22.5792 MHz
Other combinations reserved
SCLK2 = 16.9344 MHz
Reserved
Set to 0
Reserved
Set to 0
11
1 = Mode 1
00 = 48 kHz
01 = Not
Allowed
10 = 32 kHz
11 = 44.1 kHz
0 = 256 f
S
1 = 384
f
S
0 = Normal
1 =
f
NOMINAL
2
0 = 22.5792 MHz
1 = 512 f
S2
NOTES
1
Default Setting
2
In Mode 1, Frequency Double affects SCLK1 always and SCLK2 in 512
f
S
mode.
PLL CLOCK SYSTEM
The PLL clock system is expected to be run from a 27 MHz
master clock supplied by the on-board crystal oscillator or an
external source connected to XIN. With the MCLK mode set
to Output, the 27 MHz clock is buffered out to the MCLK
pin. When set to Input, this pin is the 256 f
S
master clock input
for the DAC. SCLK0 is always set to 33.8688 MHz. SCLK1 is
intended to be used as a master audio clock and will be a multiple
of the sample rate set in the PLL control register (see Table III).
In Mode 0 (Bit 8), it can be set to 512 or 768 times either
44.1 kHz or 48 kHz. SCLK2 will be 16.3944 MHz (384
44.1 kHz). In Mode 1, SCLK1 can be set to 256, 384, 512,
or 768 times 32 kHz, 44.1 kHz, or 48 kHz. SCLK2 can be
set to a constant 22.5792 MHz (512 44.1 kHz) or 512 f
S
.
There are two loop filter pins, LF0 and LF1. They should each
be bypassed to PVDD by a network consisting of a 33 nF capaci-
tor
in series with a 750
resistor, paralleled with a 1.8 nF capacitor.
The 27 MHz Master Clock oscillator should have a crystal cut for
an 18 pF load connected between XIN and XOUT, with 22 pF
capacitors connected from XIN and XOUT to PGND.
Table II. DAC Volume Registers
Bit 15:2
Volume
14 Bits, Unsigned
14 Bits, Unsigned
Bit 1:0
SPI Register Address
00 = Left Volume
10 = Right Volume
Default is full volume
RESET/POWER-DOWN
RESET
will set the control registers to their default settings. The
chip should be reset on power-up. After reset is deasserted, the
part will come out of reset on the next rising LRCLK.
SERIAL CONTROL PORT
The AD1958 has an SPI-compatible control port to permit
programming the internal control registers for the PLL and DAC.
The DAC output levels may be independently programmed
by means of an internal digital attenuator adjustable in 16384
linear steps.
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PDF描述 |
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| AD1958 | PLL/Multibit DAC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1958YRSRL | 制造商:Analog Devices 功能描述:DAC 2-CH Delta-Sigma 24-bit 28-Pin SSOP T/R 制造商:Analog Devices 功能描述:DAC 2CH DELTA-SIGMA 24BIT 28SSOP - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:HIGH PERFORMANCE PLL/MULTIBIT DAC - Bulk |
| AD1959 | 制造商:AD 制造商全稱:Analog Devices 功能描述:PLL/Multibit DAC |
| AD1959YRS | 制造商:Rochester Electronics LLC 功能描述:HIGH PERFORMANCE DAC,105DB DYNAMIC RANGE - Bulk 制造商:Analog Devices 功能描述: |
| AD1959YRSRL | 制造商:Analog Devices 功能描述:DAC 2-CH Delta-Sigma 24-bit 28-Pin SSOP T/R 制造商:Rochester Electronics LLC 功能描述:HIGH PERFORMANCE DAC,105DB DYNAMIC RANGE - Tape and Reel |
| AD1959YRSZRL | 制造商:Analog Devices 功能描述:DAC 2-CH Delta-Sigma 24-bit 28-Pin SSOP T/R |
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