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參數(shù)資料
| 型號： | AD1958 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | PLL/Multibit DAC |
| 中文描述： | 鎖相環(huán)/多比特DAC的 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 135K |
| 代理商： | AD1958 |
REV. 0
–3–
AD1958
TEMPERATURE RANGE
Min
Typ
Max
Unit
°
C
°
C
°
C
Specifications Guaranteed
Functionality Guaranteed
Storage
25
–40
–55
+105
*
+125
NOTE
*
105
°
C ambient guaranteed for a 4-layer board, two 1 oz. planes, two 2 oz. signal layers. Derate to 85
°
C for 2-layer board, 2 oz. layers.
Specifications subject to change without notice.
POWER
Min
Typ
Max
Unit
Supplies
Voltage, Analog Digital PLL
Analog Current
Digital Current
PLL Current
Dissipation
Operation—All Supplies
Operation—Analog Supply
Operation—Digital Supply
Operation—PLL Supply
Power Supply Rejection Ratio
1 kHz 300 mV p-p Signal at Analog Supply Pins
20 kHz 300 mV p-p Signal at Analog Supply Pins
4.50
5
36
25
30
5.50
41
29
34
V
mA
mA
mA
455
180
125
150
540
mW
mW
mW
mW
–60
–50
dB
dB
Specifications subject to change without notice.
DIGITAL FILTER CHARACTERISTICS
Sample Rate (kHz)
Pass Band (kHz)
Stop Band (kHz)
Stop Band Attenuation (dB)
Pass Band Ripple (dB)
±
0.0002
±
0.0002
±
0.0005
0/–0.04 (DC–21.8 kHz)
0/–0.5 (DC–65.4 kHz)
0/–1.5 (DC–87.2 kHz)
44.1
48
96
192
DC–20
DC–21.8
DC–39.95
DC–87.2
24.1–328.7
26.23–358.28
56.9–327.65
117–327.65
75
75
75
60
Specifications subject to change without notice.
GROUP DELAY
Chip Mode
INT8
×
Mode
INT4
×
Mode
INT2
×
Mode
Group Delay Calculation
f
S
48 kHz
96 kHz
192 kHz
Group Delay
Unit
μ
s
μ
s
μ
s
24.625/f
S
15.75/f
S
14/f
S
513
164
72.91
Specifications subject to change without notice.
DIGITAL TIMING (Guaranteed over –40
°
C to +105 C, AVDD = DVDD = PVDD = 5.0 V 10%)
Min
Unit
t
DMP
t
DML
t
DMH
t
DBH
t
DBL
t
DBP
t
DLS
t
DLH
t
DDS
t
DDH
t
RSTL
MCLK Period (FMCLK = 256
×
FLRCLK)
MCLK LO Pulsewidth (All Modes)
MCLK HI Pulsewidth (All Modes)
BCLK HI Pulsewidth
BCLK LO Pulsewidth
BCLK Period
LRCLK Setup
LRCLK Hold (DSP Serial Port Mode Only)
SDATA Setup
SDATA Hold
RST LO Pulsewidth
54
15
10
20
20
60
20
20
15
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Specifications subject to change without notice.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD1959YRSRL | PLL/Multibit DAC |
| AD1959 | ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86% |
| AD1959YRS | PLL/Multibit DAC |
| AD1974 | 4 ADC with PLL, 192 kHz, 24-Bit Codec |
| AD1974YSTZ | 4 ADC with PLL, 192 kHz, 24-Bit Codec |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1958YRS | 制造商:Rochester Electronics LLC 功能描述:HIGH PERFORMANCE PLL/MULTIBIT DAC - Bulk 制造商:Analog Devices 功能描述: |
| AD1958YRSRL | 制造商:Analog Devices 功能描述:DAC 2-CH Delta-Sigma 24-bit 28-Pin SSOP T/R 制造商:Analog Devices 功能描述:DAC 2CH DELTA-SIGMA 24BIT 28SSOP - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:HIGH PERFORMANCE PLL/MULTIBIT DAC - Bulk |
| AD1959 | 制造商:AD 制造商全稱:Analog Devices 功能描述:PLL/Multibit DAC |
| AD1959YRS | 制造商:Rochester Electronics LLC 功能描述:HIGH PERFORMANCE DAC,105DB DYNAMIC RANGE - Bulk 制造商:Analog Devices 功能描述: |
| AD1959YRSRL | 制造商:Analog Devices 功能描述:DAC 2-CH Delta-Sigma 24-bit 28-Pin SSOP T/R 制造商:Rochester Electronics LLC 功能描述:HIGH PERFORMANCE DAC,105DB DYNAMIC RANGE - Tape and Reel |
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