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參數(shù)資料
| 型號(hào)： | AD1955YRSRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPACER NYLON #2 SCREW 15/16,1 |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
| 封裝： | PLASTIC, SSOP-28 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 259K |
| 代理商： | AD1955YRSRL |
AD1955
OPERATING FEATURES
Serial Data Input Port
The AD1955’s flexible serial data input port accepts standard PCM audio data and external digital filter output data in twos-
complement, MSB-first format in PCM/External digital filter mode and a dedicated SACD serial port accepts DSD bit-stream data in
SACD mode. If the PCM mode is selected by control register 0 bit12 and 13, the left channel data field always precedes the right
channel data field. The serial data format and word length in PCM mode are set by the mode select bits (bits 4 and 5 and bits 2 and 3,
respectively) in the SPI control register.
In all data formats except for the right-justified mode, the serial port will accept an arbitrary number of bits up to a limit of 24 (extra
bits will not cause an error, but they will be truncated internally). In Right-justified mode, control register 0, bits 2 and 3 are used to
set the word length to 16, 18, 20, or 24 bits. The default on power up is 24-bit, I2S.
In the external digital filter mode, selected by control register 0 bit 12 and 13, bits 2 and 3 are used to set the word length to 16, 18, 20
or 24 bits and the format is set with bits 4 and 5. For a burst-mode clock, the format should be set to Left-justified. DSP mode is not
used. The LRCLK is always falling-edge active. The default on power-up is 24-bit mode in PCM and external digital filter mode.
In SACD mode, selected by control register 0, bit 12 and 13, the SACD port will accept a DSD bit-stream.
When the SPI Control Port is not being used, the SPI pins (24, 25 and 26) should be tied to DGND or DVDD.
Serial Data Format in PCM mode
The supported formats are shown in Figure 1. For detailed timing, see Figure 2.
In Left-justified mode, LRCLK is HIGH for the left channel, and LOW for the right channel. Data should valid on the rising edge of
BCLK. The MSB is left-justified to an LRCLK transition, with no MSB delay.
In I
2
S mode, LRCLK is LOW for the left channel, and HIGH for the right channel. Data should be valid on the rising edge of BCLK.
The MSB is left-justified to an LRCLK transition but with a single BCLK period delay.
In DSP serial port mode, LRCLK must pulse HIGH for at least one bit clock period before the MSB of the left channel is valid, and
LRCLK must pulse HI again for at least one bit clock period before the MSB of the right channel is valid. Data should be valid on the
falling edge of BCLK. The DSP serial port mode can be used with any wordlength up to 24 bits.
In this mode, it is the responsibility of the DSP to ensure that the left data is transmitted with the first LRCLK pulse after RESET, and
that synchronism is maintained from that point forward.
In Right-justified mode (16 bits shown), LRCLK is HIGH for the left channel, LOW for the right channel. Data is valid on the rising
edge of BCLK.
In normal operation, there are 64 bit clocks per frame (or 32 per half-frame). When the SPI wordlength control bits (bits 2 and 3 in
control register 0) are set to 24 bits (0:0), the serial port will begin to accept data starting at the 8
th
bit clock pulse after the LRCLK
transition. When the word length control bits are set to 20-bit mode, data is accepted starting at the 12
th
bit clock position. In 18-bit
mode, data is accepted starting at the 14
th
bit clock position. In 16-bit mode, data is accepted starting at the 16
th
bit clock position.
These delays are independent of the number of bit clocks per frame, and therefore other data formats are possible using the delay
values described above.
Note that the AD1955 is capable of a 32 X Fs BCLK frequency “packed mode” where the MSB is left-justified to an LRCLK
transition, and the LSB is right-justified to the opposite LRCLK transition. LRCLK is HIGH for the left channel, and LOW for the
right channel. Data is valid on the rising edge of BLCK. Packed mode can be used when the AD1955 is programmed in left or right-
justified mode.
Serial Data Format in External Digital Filter mode
In the external digital filter mode, the AD1955 will accept up to 24 bits serial, twos compliment, MSB first data from an external
digital filter, an HDCD decoder or a general purpose DSP. If the external digital filter mode is selected by control register 0, bits 12
and 13, pins 2 to 5 are assigned as the word clock input (EF_WCLK, Pin 2) , bit clock input (EF_BCLK, Pin 3), left channel data input
(EF_LDATA, Pin 4) and right channel data input (EF_RDATA, Pin 5) respectively to accept 8fs (48 kHz), 4fs (96kHz) or 2fs (196
kHz) over-sampled data.
-6-
Rev. PrF
PRELIMINARY TECHNICAL DATA
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| AD1959YRS | 制造商:Rochester Electronics LLC 功能描述:HIGH PERFORMANCE DAC,105DB DYNAMIC RANGE - Bulk 制造商:Analog Devices 功能描述: |
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